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Design of sample and hold with CMOS

Discussion in 'General Electronics Discussion' started by sps101, May 24, 2016.

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  1. sps101

    sps101

    2
    0
    May 24, 2016
    Hello,
    I am working on a project to design a sample and hold to meet the following specifications:
    Input frequency: 100MHz-500MHz
    Sampling Rate: 2GS/s
    VDD= 1.1V
    signal voltage range = 0.5V peak-peak

    I am using cadence with umc 65 technology.

    I am having a small issue when designing the sample and hold. I have used the open-loop architecture for fast switching and lower power. It is a mix of complementary input switch(NMOS AND PMOS) and a bottom plate switch as well.

    I am getting some pedestal errors and sampling errors(error between original signal and sampled signal at the instant of sampling). I would like to know what is the acceptable range for the pedestal and sampling errors. Also, is there a way to reduce these errors ? The max pedestal error i am getting is 18mV. Max sampling error is 15mV
     

    Attached Files:

  2. Harald Kapp

    Harald Kapp Moderator Moderator

    11,014
    2,506
    Nov 17, 2011
    I guess that's up to you or your application, respectively. 18mV at 500mVpp is 3.6%, a little less than 5 bit accuracy.
    For n-bit accuracy your sampling error can be calculated by Verror=0.5V* 1/2^n where n is the number of bits.

    Use a larger sampling capacitor or smaller transistors to reduce charge injection.
     
  3. sps101

    sps101

    2
    0
    May 24, 2016
    The sample and hold will be attached to a 4-bit flash adc. The end product is a digital transceiver.
    So for a 4-bit ADC, the LSB is around 0.5/2^4 = 31mV. Currently the error of 18mV is almost 0.5LSB . I am worried if this will cause any problems.

    Is that an acceptable accuracy?
     
  4. Harald Kapp

    Harald Kapp Moderator Moderator

    11,014
    2,506
    Nov 17, 2011
    You'll have to answer that yourself. Is it acceptable to you?

    Answer this question by looking at the system response. How will it change in the presence of the error?

    Taking into account that the ADC ads at least 0 .5 LSB quantizing error your total error is 1 LSB, not taking into account other factors.

    Another path you could choose: Amplify the signal e.g. by a factor of 10. Since the error voltage due to charge injection will not rise by 10, your signal to noise ratio increases approx. by 10, too. Then perform the S&H operation and, if required, divide the sampled signal by 10 (resistive divider). This will divide the error voltage by 10, too, so the signal to noise ratio after sampling is higher than with the original 0.5V signal.
    You'll have to adapt the supply and control voltages to deal with the higher signal voltage.
     
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