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depletion mode pmos for ultra simple logic level translation

Discussion in 'Electronic Design' started by Simon S Aysdie, May 14, 2007.

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  1. Does it exist? Would it work? Could it be extremely cheap? Does
    anyone make a "small" surface mount pmos depletion device at all?

    Vgs_off of "regular" JFET parts like a MMBFJ271 go up to 4.5 V, which
    is too high. Or for J270, the min I_DSS is too low.

    --- GND
    <0,3.3>V O------G||
    +------O <-5,0> V
    \ 1k
    ~ -5V
  2. Supertex may have something like that.
  3. John Larkin

    John Larkin Guest

    I don't know of any.

    How about common-base?

    pnp b----gnd

    It's not perfect, admittedly. But the pnp would be very cheap.

  4. MooseFET

    MooseFET Guest

    Better yet common emitter:

    Modified drawing:
    The modified works better with logic that pulls down better than up.
    You don't want the resistors to be equal. They should be scaled to
    make the gain to get the required output swing.

    This circuit also has a nice feature that it is a near constant output
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