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Delta-sigma ADC question

S

soos

Jan 1, 1970
0
Hello,

I am looking for an ADC 16+ bit resolution that would sample 64 chanels
at the
rate of 25 Khz each. switching is planned to be done with a mux.

I have heard that the sigma delta ADCs are not appropriate for this
task

Questions are:

1.If indeed they are'nt ,can some one explain why?
2.if not can any one point a specific SD ADC that can stand they rates
mentioned.

Thanks in advace,
Marc.
 
M

Mark Borgerson

Jan 1, 1970
0
Hello,

I am looking for an ADC 16+ bit resolution that would sample 64 chanels
at the
rate of 25 Khz each. switching is planned to be done with a mux.

I have heard that the sigma delta ADCs are not appropriate for this
task

Questions are:

1.If indeed they are'nt ,can some one explain why?
2.if not can any one point a specific SD ADC that can stand they rates
mentioned.

Delta sigma converters generally require several times as long to
get a stable output when switching inputs with a multiplexer because
the internal digital filters require settling time.

You are looking at collecting 64 x 25000 samples per second or
1.6MSamples per second. Multiply that times 3 for the extra settling
time, and you're going to need a REALLY fast clock for the converter,
and a very fast multiplexer.

64 channels times 25KHz is a problem better suited to multiple
faster converters. The RADAR, SONAR, and ultrasound folks might
have a solution, but it won't be cheap!

Mark Borgerson
 
B

Ban

Jan 1, 1970
0
soos said:
Hello,

I am looking for an ADC 16+ bit resolution that would sample 64
chanels at the
rate of 25 Khz each. switching is planned to be done with a mux.

I have heard that the sigma delta ADCs are not appropriate for this
task

Questions are:

1.If indeed they are'nt ,can some one explain why?
2.if not can any one point a specific SD ADC that can stand they rates
mentioned.

SD-ADCs have a latency(pipeline delay) because the conversion needs a couple
of clock cycles to be finished. Look in the datasheet, usually 3 to 24
samples are needed. You can multiplex the input, but then have to wait those
cycles until a meaningful data is output. The problem with so many inputs
will be that now the output data has to be really fast, in fact the rate
would need to be 64 * 25k * delay. The AD10678 would be possible, with 11
cycles delay you will need 17.6MHz clock, well below the 80MHz capability,
but the price...
A much better decision would be a SAR-based converter, which do not have a
pipeline delay. Maybe you could come along with one or two AD7655, which has
already a 4:1 Input mux, so your analog switches are reduced. 2 channels are
sampled simultaneously, which might be of importance for certain
measurements.
Thanks in advace,
Marc.
welcome
 
C

CBFalconer

Jan 1, 1970
0
soos said:
I am looking for an ADC 16+ bit resolution that would sample 64
chanels at the rate of 25 Khz each. switching is planned to be
done with a mux.

I have heard that the sigma delta ADCs are not appropriate for
this task

Questions are:

1.If indeed they are'nt ,can some one explain why?
2.if not can any one point a specific SD ADC that can stand they
rates mentioned.

Delta modulation generally follows changes in the input signal,
with significant limitations on the slew rate. A mux implies
wholesale alteration in that value, and thus is not suitable in
front of delta modulation.
 
P

Paul Keinanen

Jan 1, 1970
0
I am looking for an ADC 16+ bit resolution that would sample 64 chanels
at the rate of 25 Khz each. switching is planned to be done with a mux.

I have heard that the sigma delta ADCs are not appropriate for this task

In any sampled systems, the input spectrum must be limited to below
fs/2 in order to avoid aliases.

In SD ADCs, this bandwidth limitation is more or less inherent due to
the way the SD converter works and very little or no external low pass
filtering is required.

In a multiplexed system, the multiplexer becomes the sampler and the
low pass filtering has to be moved in front on the multiplexer and
implemented on _every_ input channel. Implementing 64 analog low pass
filters with precision resistors and capacitors or SCFs will also add
quite a lot to the system cost.

With current low cost of SD ADCs, using 64 separate ADCs might be more
cost effective than using a super fast ADC, a multiplexer and signal
conditioning for all the 64 input channels.

Paul
 
R

Randy Yates

Jan 1, 1970
0
Hi Mark,

Maybe you can enlighten me a bit here. Back in my old school/analog
days, I was taught that settling time is inversely proportional to
bandwidth. If I have a Fn Hz channel (from sampling at 2*Fn samples
per second), then why wouldn't the settling time of an input be the
same whether I used delta sigma or flash converter techniques?

I've heard this flavor of argument for years (decades?) against
using delta sigma converters in multi-channel systems. It must
be true - the folks who have used them would know (I have not). But
as I've just queried, there's something that doesn't seem to add up,
in my view.

--RY
 
V

Ville Voipio

Jan 1, 1970
0
Hello,

I am looking for an ADC 16+ bit resolution that would sample 64 chanels
at the
rate of 25 Khz each. switching is planned to be done with a mux.

It is rather difficult to find a sigma-delta ADC for that kind
of sampling frequency even for a single channel. Of course,
many inexpensive audio converters claim something like
"192 ks/s, 24 bits", but this is not the complete truth.

If you want to use such a converter in a multiplexed system,
you'll face the fact that the bandwith limitation (96 kHz)
effectively limits the settling time when multiplexing.

The worst case is when you have two multiplexed signals
which alternate between minimum and maximum. The square
wave produced this way has very significant high frequency
components. If you want to sample this signal down to
16 bits, the bandwidth has to be way larger than the multiplexing
frequency.

So, the first problem is the bandwidth-limiting nature of
sigma-delta converters. Other converter types (SAR, flash)
don't have this problem, their bandwidth may be much wider
than the sampling frequency (which in many cases is a problem
per se).

Another significant problem with sigma-delta converters
is their bad DC behaviour. The "el cheapo" audio converters
have rather impressive dynamic performance, but when it comes
to measuring DC levels, there may be hundreds of LSBs of
error and drift, as those parameters are insignificant in
audio processing.

There are fast DC-accurate sigma-deltas as well. For example,
the TI (BB) ADS1606 seems to offer 16 bits at 5 Ms/s and
2.45 MHz bandwidth. Oh, the price is $30 each, and you'd still
need many of these in parallel (check the data sheet to
get the idea of the settling time).

There are some less expensive converters with dozens of
kilosamples per second. However, they could sample only one
channel at a time, and the price is still well above
that of an inexpensive audio sigma-delta.

I'd recommend using the approach of one converter per channel.
This makes the sampling requirements much easier. If you want
to sample something at 64 x 25 kHz = 1.6 MHz at 16 bits, the
input impedance has to be low, but at 25 kHz there should be
no problems.

If you really want to multiplex, then SAR converters are better.
There are 16-bit SAR converters with megasample-range throughput.
Using one of these could possibly solve the problem with a
single converter and a huge multiplexer. (Beware, there are even
SAR converters with poor DC performance!)

The solution this way would be less expensive than with per-channel
converters, but the design is more complicated (multiplexers,
buffers, etc. with 16-bit accuracy). In any case, you'll need
to study the converter data very carefully, as very often
the datasheets are rather shy when it comes to the deficiencies
of the converters.

- Ville
 
V

Ville Voipio

Jan 1, 1970
0
Maybe you can enlighten me a bit here. Back in my old school/analog
days, I was taught that settling time is inversely proportional to
bandwidth. If I have a Fn Hz channel (from sampling at 2*Fn samples
per second), then why wouldn't the settling time of an input be the
same whether I used delta sigma or flash converter techniques?

If the bandwidth is the same, then there is no difference between
the converters.

But if you take a typical SAR converter, its analog bandwidth
(before the sampling stage) is typically much larger than the
sampling rate. For example, the AD7476 (1 Ms/s, 12-bit SAR ADC)
has 1 Ms/s maximum sampling rate and 6.5 MHz full-power (3 dB)
bandwidth. This bandwidth will give LSB settling at the maximum
sampling rate.

On the other hand, the (pseudo-analog) bandwidth of a sigma-delta
is almost exactly Fs/2. This means in this case there is 1:10
ratio between the bandwidths, and this makes the difference in
settling time.

- Ville
 
J

John Woodgate

Jan 1, 1970
0
I read in sci.electronics.design that Randy Yates
Ville Voipio said:
sigma delta sigma delta sigma delta [...]

It's "delta sigma".

Both terms are used. I once thought they were different configurations,
but it appears not. OTOH, the digma-selta converter has a higher alcohol
content.
 
A

Andre

Jan 1, 1970
0
Additionally, you might have to deal with delays. Typical delay times
between analog input and digital output of delta-sigma ADs are around 15
samples! This might make synching mux timing and sampled data hard to do.

Best regards,

Andre
 
C

CBFalconer

Jan 1, 1970
0
Randy said:
Maybe you can enlighten me a bit here. Back in my old
school/analog days, I was taught that settling time is inversely
proportional to bandwidth. If I have a Fn Hz channel (from
sampling at 2*Fn samples per second), then why wouldn't the
settling time of an input be the same whether I used delta sigma
or flash converter techniques?

I've heard this flavor of argument for years (decades?) against
using delta sigma converters in multi-channel systems. It must
be true - the folks who have used them would know (I have not).
But as I've just queried, there's something that doesn't seem
to add up, in my view.

Please don't toppost. Your answer belongs after, or intermixed
with, the material you quote, with immaterial matter snipped out.

First, consider what a delta demodulator is:

1 bit signal ----1 bit register-----integrator----->out analog
^
clock ---------------|

simple, huh? Now, how do you make a delta encoder?

clock-------------------------------------+
|
input signal--->-|----------+ v
|comparator|---->-1 bit register-+->out bits
+-->-|----------+ |
| |
+---<-----the same demodulator-<------+

still simple, huh. The demodulator is the integrator. All that
has been added is a single comparator and feedback. The integrator
is an op-amp with one resistor and one capacitor. Any failure to
match time constants shows up as a gain factor.

What it encodes is simple - is the input higher or lower than the
output at any given (clocked) moment. The integrator has to
operate peacefully throughout the clock period, so there is nothing
to multiplex, except possibly the digital transmission path.

That is also why delta systems always have an output at 1/2 the
clock frequency. They are never stable at a voltage level.

Contrast that with a flash, or almost any conventional ADC. It
takes a sample, possibly holds it, and generates a multi-bit
representation of that sample. The delta system generates a one
bit comparison, at a higher clock rate.
 
V

Ville Voipio

Jan 1, 1970
0
It's "delta sigma".

Analog uses "sigma delta", Linear uses "delta sigma", TI/BB
uses "delta sigma". Maxim does not know which one to use:

http://www.maxim-ic.com/appnotes.cfm/appnote_number/1870

IIRC, Linear tried to make a big difference between delta-sigma
and sigma-delta when LTC2400 came around. There is indeed
a theoretical difference between the two topologies, but
as the difference is rather insignificant from the user's
point of view, the two terms seem to be used as synonyms.

Actually, it would be more precise to talk about "oversampling"
converters, because that's what makes the difference. Not the
actual converter topology or modulator order.

- Ville
 
R

Rob Gaddi

Jan 1, 1970
0
Ville said:
Actually, it would be more precise to talk about "oversampling"
converters, because that's what makes the difference. Not the
actual converter topology or modulator order.

- Ville

Not exactly. The pole in the feedback loop of a delta-sigma converter
serves to take the nominally white quantization noise power and blue
shift it into the higher frequencies, which if your mixed signal system
is designed correctly will then be out of band from your signal, such
that the quantization noise can be filtered and decimated out. This is
in contrast to just taking say an SAR, oversampling by N, filtering, and
decimating, which doesn't perform this noise shaping because it doesn't
have the feedback.
 
J

Jerry Avins

Jan 1, 1970
0
CBFalconer said:
... The delta system generates a one
bit comparison, at a higher clock rate.


Then that gets low-pass filtered, smoothing the choppy result and adding
precision -- extra bits -- by averaging. The filter adds delay and needs
to be flushed and refilled whenever the MUX selects a new input.

Jerry
 
J

John Larkin

Jan 1, 1970
0
Not exactly. The pole in the feedback loop of a delta-sigma converter
serves to take the nominally white quantization noise power and blue
shift it into the higher frequencies, which if your mixed signal system
is designed correctly will then be out of band from your signal, such
that the quantization noise can be filtered and decimated out. This is
in contrast to just taking say an SAR, oversampling by N, filtering, and
decimating, which doesn't perform this noise shaping because it doesn't
have the feedback.


I've never understood that. You'll have to explain it to me some day.

John
 
M

Mark Borgerson

Jan 1, 1970
0
Hi Mark,

Maybe you can enlighten me a bit here. Back in my old school/analog
days, I was taught that settling time is inversely proportional to
bandwidth. If I have a Fn Hz channel (from sampling at 2*Fn samples
per second), then why wouldn't the settling time of an input be the
same whether I used delta sigma or flash converter techniques?

The simple explanation seems to be that there are internal digital
filters that have to settle before the output is valid. The number
and kind of internal filters determines the response to a step
input on the signal.

I'm sure someone else has (or will) explain in greater detail. If
not, look into the data sheet on the CS5534 (a sigma-delta
converter with multiplexe inputs).
I've heard this flavor of argument for years (decades?) against
using delta sigma converters in multi-channel systems. It must
be true - the folks who have used them would know (I have not). But
as I've just queried, there's something that doesn't seem to add up,
in my view.

If it was easy, no one would pay us the big bucks for solving these
problems! ;-)


<SNIP>

Mark Borgerson
 
J

John Woodgate

Jan 1, 1970
0
I read in sci.electronics.design that Randy Yates
Back in my old school/analog days, I was taught that settling time is
inversely proportional to bandwidth.

That applies to minimum-phase networks. Anything with a delay in it is
in principle not minimum-phase and there is no general relation between
settling time and bandwidth.
 
J

John Woodgate

Jan 1, 1970
0
I read in sci.electronics.design that John Larkin
I've never understood that. You'll have to explain it to me some day.

Look for Audio Engineering Society papers by S Lipshitz and J
Vanderkooy. If you are like me, you still won't understand it. (;-)
 
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