Delaying a logic signal?

[Philip Pemberton]

Hi,
I'm designing a simple (ha!) digital oscilloscope that should theoretically
be able to sample up to 80MHz with two A/D converters (giving an effective
frequency of around 160 MHz). I'd also like to design this device so I can
expand it with more converters later on (up to four). What I need to know is
how to delay a logic signal (the /SAMPLE line) so that it's 90 degrees out of
phase. Then I need another two in addition to that - 180deg and 270deg. The
signal needs to be as close to 50% as possible. How could I do this? None of
my textbooks seem to cover this sort of thing.
The idea is that I'll have multiple ADCs sampling at different times, one
after the other. The data will end up in a FIFO, which will then be read by
the PC via the ISA bus.
I'm also going to need a programmable clock divider that can provide
various frequencies to the ADCs. I guess this would be best done with a
counter and a multiplexer?

Thanks.

 

[CWatters]

Lots of ways..

Try using a counter to steer the master Sample signal to the output of a 2
to 4 decoder.

This produces a pulse on each output in turn eg

1000
0100
0010
0001
1000
0100
etc

 

[CWatters]

Actually you want to be able to control the timing of the sample pulses more
accuratly than that. Ideally you want to be able to adjust the interval
between triggering and sampling perhaps a down to a nS?. That way you can
sample repetitive signals (only) that are much faster than the sample rate.
eg you can display a 200MHz sin wave even ifyou only have 85Mhz ADC's.

Do a google for "PC oscilloscope" and read about existing designs including
at least two kits that are available.

 

[Philip Pemberton]

In message <[email protected]>

- Either use a higher frequency master clock (4x80MHz for example) and
divide it to generate the clocks driving each ADC. Usually done inside a
small FPGA

That sounds like the best (cheapest) option - get an SRAM FPGA (or an EEPLD)
and put the glue logic inside it. I don't mind being stuck at 10nS - my
Tek466 only goes down to .05uS anyway.

However of course the remaining part of the circuit should match this time
resolution (calibrated track lenghts, controlled impedance, etc).

That's going to be, er... "fun"...

Thanks.