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Delay without affecting pulse width

Discussion in 'Electronic Basics' started by BR, Mar 7, 2005.

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  1. Kitchen Man

    Kitchen Man Guest

    I guess I didn't explain myself clearly. I don't think there is a
    system clock, so to use this approach, a system clock has to be
    developed and synchronized to the release pulse.
     
  2. Guest

    The clock doesn't need to be synchronized with anything. Free running
    would be fine. The 'downside' is a 2 uSec window with a 500 KHz clock.
    Use a bigger FIFO and faster clock for a smaller window. I got the
    impression from earlier posts that the exact timing wasn't critical.
    Think of it more like a crude 1 bit recorder/player.
    GG
     
  3. John Fields

    John Fields Guest

    ---
    The easiest way, I think, would be to use something like an HC123 or a
    4538. Use the first section to generate the delay and to trigger the
    second section after that delay. The output of the second section
    will be the pulse you want and, if you use this approach, will also be
    adjustable.

    See "Delay without affecting pulse width" on
    alt.binaries.schematics.electronic for a schematic and circuit
    description.
     
  4. John Fields

    John Fields Guest

  5. Jamie

    Jamie Guest

    i think what your looking for is a continous running clock that
    inputs it's pulses to an AND gate. when the other input is on, the
    pulse will appear on the output of the AND gate in sync because there
    is no initial starting of an OSC/timer
    etc.

    is that what your looking for ?
     
  6. BR

    BR Guest

    I have some 4528 Thanks for the schematic.

    Ben

    --
     
  7. Guest

    Nope, even simpler than that. No gate required because no
    synchronization is required. But you're right that the clock would need
    to run continuously. The pulse to be delayed is applied to the input of
    the shift register. I assume the logic families are compatible I.E.
    you're not trying to connect ECL into TTL without the proper interface.
    The delayed pulse(s) extracted some number of shift cycles later from
    one or more 'taps'. This is nothing more than a digital equivalent of
    the old analog CCD audio chips from the '70s.
    GG
     
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