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Delay in Verilog Programme

Discussion in 'Microcontrollers, Programming and IoT' started by mrbazooka, Nov 2, 2011.

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  1. mrbazooka

    mrbazooka

    2
    0
    Oct 19, 2011
    I need delay for 5seconds in the coding after the detection.




    module trial(clk, a, b, RCServo_pulse);
    input clk;
    input a, b;
    output RCServo_pulse;
    reg [7:0] RxD_data_reg;
    always @(posedge clk)
    begin
    if ((~a) & (~b)) begin
    RxD_data_reg <= 8'b00000000;
    end
    else
    if (((~a) & b) | (a & (~b))) begin
    RxD_data_reg <= 8'b11111100;
    end
    else
    if (a & b)
    #10000 begin
    RxD_data_reg <= 8'b10000000;
    end
    end

    parameter ClkDiv = 195; // 50000000/1000/256 = 195.31

    reg [7:0] ClkCount;
    reg ClkTick;
    always @(posedge clk) ClkTick <= (ClkCount==ClkDiv);
    always @(posedge clk) if(ClkTick) ClkCount <= 0; else ClkCount <= ClkCount + 1; /* reset ClkCount when 1 tick
    else continue counting*/
    reg [11:0] PulseCount;
    always @(posedge clk) if(ClkTick) PulseCount <= PulseCount + 1; // for each tick increment pulsecount 1

    // make sure the RCServo_position is stable while the pulse is generated
    reg [7:0] RCServo_position;
    always @(posedge clk) if(PulseCount==0) RCServo_position <= RxD_data_reg; /*first time through Pulsecount output width of pulse
    thereafter output 0 until time for next pulse*/
    reg RCServo_pulse;
    always @(posedge clk)
    RCServo_pulse <= (PulseCount < {4'b0001, RCServo_position});
    endmodule
     
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