Deglitching a DAC

[Spehro Pefhany]

Any clever ideas on getting rid of glitches in a high precision DAC
output? Update rate is a fixed rate, probably in the 10-100kHz range,
and I'd like to keep the glitches (especially variation in glitches)
to << 25ppm, preferably < 5ppm. A S&H with a low charge injection
switch?

 

[Spehro Pefhany]

I'm a fan of dual-gate MOSFETs for that sort of job, because the charge
injection is so low.

Cheers

Phil Hobbs

Is the idea to use an opposite going pulse on the second gate to
compensate for the capacitive coupling?

 

[Nico Coesel]

Any clever ideas on getting rid of glitches in a high precision DAC
output? Update rate is a fixed rate, probably in the 10-100kHz range,
and I'd like to keep the glitches (especially variation in glitches)
to << 25ppm, preferably < 5ppm. A S&H with a low charge injection
switch?

What kind of DAC is it? IIRC the better DACs have a latch enable pin
which sets the new value for a bits in 1 go. Or does the DAC have that
and is still misbehaving?

 

[Spehro Pefhany]

What kind of DAC is it? IIRC the better DACs have a latch enable pin
which sets the new value for a bits in 1 go. Or does the DAC have that
and is still misbehaving?

It's not a digital thing. There's an output glitch whenever the code
is updated. The size depends on the number of switches changing, so
it's almost independent of the output value (eg. 0x3F..F changing to
0x40..0 is only one LSB but most of the switches change, while
0x40..00 to 0x40..01 is the same change single LSB but only a single
switch changes.

 

[Spehro Pefhany]

LTC makes some 16-bit internally-deglitched DACs.

Or use a fast dac and lowpass filter it. That will help kill digital
clock+data feedthrough, which can be as big a problem as pure
glitches.

A delta-sigma dac will have low glitch energy, but maybe not enough
bandwidth.

It's an Analog '5791- pretty much a real 20 bits.

 

[Spehro Pefhany]

No, you bypass the second gate, or connect it to the source via an RC.
The effective output capacitance then is about 0.02 pF or less, a good
factor of 10 less than you can get in other discrete parts.

Cheers

Phil Hobbs

So it's effectively a cascode?

 

[Spehro Pefhany]

Could you possibly digitally limit the amount of code change,
essentially digitally slew limit? I have an idea for a deglitcher but
it could only tolerate a half volt or so of voltage step.

Yes, that's certainly possible, but the update rate might have to be
juiced up.

 

[Joerg]

Yes, that's right. The cascode device is on-chip, though, so it works
better.

That's just the problem with DACs, on chip things get worse because the
miniscule remnants of digital control pulses find their way into
everything. Almost like spilled oil.

The best de-glitcher would be off chip and, most importantly,
differential. Compensating charge injection via a "counter charge" is
one of the tricks to muffle any newly induced spikes. I have always done
it in discretes but maybe the ADG12xx series switches is good enough for
Spehro's project.

 

[Jamie]

That's just the problem with DACs, on chip things get worse because the
miniscule remnants of digital control pulses find their way into
everything. Almost like spilled oil.

The best de-glitcher would be off chip and, most importantly,
differential. Compensating charge injection via a "counter charge" is
one of the tricks to muffle any newly induced spikes. I have always done
it in discretes but maybe the ADG12xx series switches is good enough for
Spehro's project.

This thread reminds of a tube of serial DACs that were ship to us by
mistake. We kept them for prosperity.

Jamie

 

[Spehro Pefhany]

Sample output after switch change, store, etc.?

Sure, that's the idea.. but the details of ppm-level S&H are where it
gets "interesting".


Best regards,
Spehro Pefhany

 

[Spehro Pefhany]

Message off into the ether.

What kind of logic are you using to drive the DAC? Is there any
relationship to the driving edge speed, or does it depend only
on the internal update signal after the data are in?

It's doing pretty much what the data sheet says it should do,
unfortunately. The glitching happens with the update.


Best regards,
Spehro Pefhany

 

[Joerg]

It's doing pretty much what the data sheet says it should do,
unfortunately. The glitching happens with the update.

You've got to re-sample it outside the chip. There is no way to push
things down to ppm levels on the same chip with the digital stuff on
there. Mainly because there's lead inductance, chatter across the
substrate, finite metal layer conductivity, inductive coupling, and all
this fun stuff. I'd consider a diff-output DAC followed by a
differential S&H. Decouple and bypass the supplies really well. Ferrite
beads and 0402 or 0603 caps are your friends here.

 

[Nico Coesel]

It's not a digital thing. There's an output glitch whenever the code
is updated. The size depends on the number of switches changing, so
it's almost independent of the output value (eg. 0x3F..F changing to
0x40..0 is only one LSB but most of the switches change, while
0x40..00 to 0x40..01 is the same change single LSB but only a single
switch changes.

Is the glitch also noticable when you change one bit? Adding more
analog stuff often means more error & noise. Could this be handled in
the digital domain by converging to the new value by flipping one bit
at a time?

 

[Spehro Pefhany]

You've got to re-sample it outside the chip. There is no way to push
things down to ppm levels on the same chip with the digital stuff on
there. Mainly because there's lead inductance, chatter across the
substrate, finite metal layer conductivity, inductive coupling, and all
this fun stuff. I'd consider a diff-output DAC followed by a
differential S&H. Decouple and bypass the supplies really well. Ferrite
beads and 0402 or 0603 caps are your friends here.

The irritating thing is that it's directly related to the switches..
and it ought to be possible to match that stuff on the chip to very
close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV
glitches on a chip (datasheet claim, so ideal conditions) on a chip
with ~100nV of RMS output noise and 1ppm linearity seems... a bit
much.

http://www.speff.com/glitch.png

 

[Spehro Pefhany]

Is the glitch also noticable when you change one bit?

Yes, it's dependent on the number of switches changing.. so as few as
one and as many as 19 switches for a single LSB output change.

Adding more
analog stuff often means more error & noise. Could this be handled in
the digital domain by converging to the new value by flipping one bit
at a time?

Nope. Although I suppose I could declare some codes personna
(numbera?) non grata and avoid the worst of them at the expense of a
bit or two resolution. 8-(

 

[Spehro Pefhany]

Yep. Trick is to make desired slew-rate, yet have precise settling.

...Jim Thompson

Not sure slew rate is the right way- the glitches look to have about
the same time-voltage area above nominal as below, so a linear filter
might be better.

 

[Spehro Pefhany]

That's where the dual-gate MOSFET comes in. They work great.

Cheers

Phil Hobbs

Sure looks nice in simulation.

 

[Joerg]

The irritating thing is that it's directly related to the switches..
and it ought to be possible to match that stuff on the chip to very
close tolerances. Maybe they'd have to trim it a bit.. but 10-20mV
glitches on a chip (datasheet claim, so ideal conditions) on a chip
with ~100nV of RMS output noise and 1ppm linearity seems... a bit
much.

http://www.speff.com/glitch.png

My very first "real" project in this direction was my masters project.
I've got to scan that stuff in some day. Anyhow, it was the design of a
CCD camera from scratch because the circuit from the CCD manufacturer
was ... ahem ... lets say, the pits. They got a measly 45dB of dynamic
range because of bad charge injection noise and such.

So I used diode quads, one for each of the three output channels. Off
the bat that bumped it to 60dB. Charge injection wasn't even measurable
anymore and we were down to the inherent noise of the CCD
"bucket-brigade" cells.

The trick: The transformers driving the sampler were carefully made not
to favor one side over the other, so any capacitive coupling would be
neutralized. I made them out of ferrite, cost almost nothing. We did
have a DC offset due to diode imbalances but that was a piece of cake to
compensate for (I just clamped it away).

If a FET switch is desired one could either look for well neutralized
mux ICs or counter-inject a charge of opposite polarity. The usual, two
bent wires near each other as a poor man's capacitor, bent with a wooden
chop stick until it's just right. A good excuse for an evening at the
Japanese restaurant.

 

[Tim Williams]

Sure. But I have an idea for a gated deglitcher, but it wouldn't
handle big voltage steps. It might work if Speff can digitally
slew-rate-limit the dac steps.

Still thinking about it.

Sounds like a diode balanced mixer with balanced CCS pull up and pull down.

Use LEDs and avoid the voltage limit.

Tim

 

[Jamie]

On Tue, 17 Jul 2012 20:28:29 -0700 (PDT),



A simple slew-rate limiter circuit might make a pretty good
deglitcher. Sort of like a lowpass filter, but with more precise
settling behavior.

What's wrong with a resetable integrator?

Jamie