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Decoupling question

Discussion in 'Electronic Design' started by [email protected], Apr 12, 2007.

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  1. Guest

    OK, so what if you're decoupling a point, like a reference pin on a
    DAC, and not a power plane. Do you use the stagger cap technique, or
    the largest value for a footprint technique?

    I really feel like starting a good decoupling thread. There hasn't
    been one for a while.

    Let me start it:
    I think decoupling with 18pf, 22pf, 33pf, 47pf, 100pf on a reference
    pin is a great technique because I can superimpose the Spice plots and
    show I'm knocking out the spikes.
     
  2. Joerg

    Joerg Guest

    That would be the "Princess on the Pea" method?

    Usually it suffices to make sure that another smaller cap takes over the
    frequency range where the larger one fizzles. For example, when it has
    to be super quiet I place a 3300pF or 4700pF right at the pin, then a
    0.1uF ceramic next to it. Size is a bit important as well. In this case,
    less is more ;-)
     
  3. Mark

    Mark Guest

    the problem with High Q caps in parallel is that the smaller cpa will
    form a parallel resonance with the parasitic inductance of the larger
    cap. The parallel resonance creates a high Z which is exactly what
    you don't want. The ESL of physically small chip caps is very low.
    It's usually best to just use a 0.1uF chip cap and call it a day.

    Mark
     
  4. Joerg

    Joerg Guest

    Well, sometimes you just have to. "Know thy capacitors". That's why I
    have an impedance analyzer in the lab and a sheet with all the data plus
    the actual capacitor taped onto the respective line on that sheet ;-)

    Another trick for really serious noise situations is to provide a small
    SMT resistor between the 0.1uF and the smaller cap.
     
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