P
PeteS
- Jan 1, 1970
- 0
I've had chips where the mfr has requested I put those low inductance
vias to the ground and power planes *in* the device pads.
I didn't, and everything worked fine, although I did take great care
with the decoupling. Obviously, that sort of thing has implications at
board reflow.
On another much earlier point, caps up to 100uF are available in
multilayer ceramic (although the 100uF are 6.3V, X7R,1210) which I have
used extensively with no problems. To my understanding, the capacitor
manufacturers are trying to increase the capacitance available, (with a
generally lower voltage range) for low voltage, high current systems.
Cheers
PeteS
vias to the ground and power planes *in* the device pads.
I didn't, and everything worked fine, although I did take great care
with the decoupling. Obviously, that sort of thing has implications at
board reflow.
On another much earlier point, caps up to 100uF are available in
multilayer ceramic (although the 100uF are 6.3V, X7R,1210) which I have
used extensively with no problems. To my understanding, the capacitor
manufacturers are trying to increase the capacitance available, (with a
generally lower voltage range) for low voltage, high current systems.
Cheers
PeteS