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Decoupling capacitor selection

Discussion in 'Electronic Design' started by Randall Nortman, Sep 14, 2005.

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  1. I have to admit to being a bit ignorant about the various types of
    capacitors available, for example NPO, X7R, etc. I believe these
    abbreviations refer to the type of dielectric used, which influences
    the properties of the capacitor. Can anybody point me to a key for
    deciphering these codes, preferrably with some information on what the
    relevant properties of the different types are?

    And what is the best type of capacitor/dielectric for basic power
    supply decoupling/bypassing on digital logic ICs (e.g.,
    microcontrollers) with clock speeds up to about 50MHz. I have often
    seen datasheets recommend two different types of capacitor in parallel
    -- is this to eliminate harmonics that would be present with only one
    type? If I have a single big 47uF capacitor between the Vcc and
    ground planes somewhere on the board, and one 0.1uF capacitor at every
    Vcc pin, does this solve the problem? What dielectric types or other
    specs should each of those have?

    I'm specifically looking for surface-mount chip-type capacitors, if
    that matters. (I suppose the 47uF should be a can-style through-hole
    capacitor, presumably electrolytic?)

    Thanks for any advice,
  2. I read in that Randall Nortman
    Any data sheet on ceramic capacitors will give you that sort of
    information. Basically NPO dielectric doesn't change its properties with
    temperature very much, but it has a lowish permittivity, so large value
    caps are physically large. X7R properties vary a lot with temperature,
    but it has higher permittivity. There are dielectrics worse than X7R for
    variation; use only with great caution.
    Not directly in parallel, because this causes the smaller value to
    resonate with the inductance of the larger one, creating a high
    impedance just where it can cause most trouble. An exception is when the
    values are VERY different , e.g. 100 uF and 100 pF.
    Not harmonics, but frequencies in general that are above the
    self-resonant frequency of the larger value. Once again, a good data
    sheet will show you all this.
    Probably; the 47 uF doesn't want to be close up to one of the 0.1 uF,
    because of the parallel resonance thing. A few cm of track between them
    usually is OK.
    The 47uF is likely to be an aluminium electrolytic. Choose a rated
    voltage at least 20% above the voltage you will apply, but not 100%
    higher. The 0.1uF can be X7R ceramic types, unless you are looking for a
    wide temperature range. Data sheet, again.
    You can get SMD aluminium electrolytics if you want.
  3. John  Larkin

    John Larkin Guest

    You can chack cap manufacturers for specs, but for bypassing, it
    doesn't matter. Any 0.1 uF ceramic cap is fine, with short leads or
    surface mount preferred for fast logic.
    There's no reason to do that. Superstition.

    That sounds fine. Dielectric type doesn't matter. If you have a
    multilayer board with solid Vcc and ground planes, you need fewer
    caps, one per each 2-8 chips maybe. I know people who don't use
    bypasses at all, and their boards work, too.
    Yes, one buggish aluminum cap is good for low-frequency load steps and
    general damping. Don't use tantalums... they explode.

    Everybody has their own strong opinions on bypassing, because almost
    anything you do will work.

  4. Richard H.

    Richard H. Guest

    FYI, something I picked up from reading on the subject ... when
    selecting a bypass capacitor value, rise time is the key variable (not
    the clock speed). The significance here being that the device may run
    at a "slower" clock, but have a rise time that's characteristic of a
    much faster clock. I gather the implication being that the fast rise
    time requires a fast change of current into the device.

    Perhaps someone can comment on this approach, and how it changes
    considering that:
    a) rise times are only stated for the outputs (which I gather might use
    a different technology from the guts of the chip)
    b) rise time internally could be faster than the output rise times,
    especially for chips that use many internal clock cycles per instruction
    or are clocked slower than rated (i.e., outputs would be able to
    transition less often and might have slower rise times as a result)

    You can get SMT electrolytics. They're mini cans with pads on the
    bottom instead of leads. Recommendations I see suggest placing a larger
    electrolytic where the power comes into the board, to offset any effects
    from the connecting cable.

  5. Joerg

    Joerg Guest

    Hello Randall,

    X7R is fine for that purpose. Just don't select the smallest possible
    size capacitor for a particular uF and voltage rating. It might have a
    dielectric that is special and few or only one manufacturer. Many of us
    have been burned by the Z5U shortage a couple decades ago. IIRC a
    chemical plant somewhere in Asia suffered an explosion and shut down. In
    consequence lots of SMT caps weren't available at all in large quantities.

    As John mentioned you might want to reconsider if your 47uF is a
    tantalum. Many of those have some rather unpleasant pathologies.
    Electrolytics, too, in that they dry out over time but at least they
    have a lower tendency to explode.

    Regards, Joerg
  6. When you are dealing with a board full of expensive logic, using the axial
    aluminium cased Tantalum Electrolytics, used in conjunction with a power
    supply with crowbar or foldback facility, is a form of protection for the
    logic devices. This is because the tantalum capacitor will go short circuit
    if the power rail voltage rises above the voltage rating of the capacitor
    by a small margin. Better to loose a tantalum than loose lots of expensive
    logic. Of course, if you are using a power supply that does not foldback or
    have crowbar shutdown then the tantalum will explode, as would any other
    electrolytic under such circumstances.
    It is worthwhile considering what your circuit is doing. I am sure that the
    chip designers will have done something to give the best possible power
    rail performance inside their device. The chip datasheet might even make
    some reccommendations regarding proper decoupling (so worth looking up in
    case they do).
    It is, essentially, the di/dt slope that becomes the major headache. That
    is why you need decoupling capacitors that are suited to the application at
    hand. Fortunately, the selection can be done with a fairly broad brush
    approach. Important factors can be ACR (yes, even for decoupling capacitors
    in high frequency/high slew rate systems) and self inductance.
    Let the chip designer worry about inside the chip. You will find that the
    I/O pins are usually heavier duty than anything they have done inside.
    Check the chip datasheet for reccommendations about decoupling.
    Inside the chip, even if the rise times are faster, the currents on the
    silicon are much less. It is a combination of current and speed of change
    that pulls the bigger spikes.

    Paul E. Bennett ....................<email://>
    Forth based HIDECS Consultancy .....<>
    Mob: +44 (0)7811-639972
    Tel: +44 (0)1235-811095
    Going Forth Safely ....EBA.
  7. David Brown

    David Brown Guest

    I would tend to think of it the other way round - pick the smallest
    package you are happy working with (0805 works well, or 0603 for higher
    density) and then find the largest capacitance value in that package in
    your voltage, price and availability range. If you are doing high speed
    stuff, aim for low ER dialectics.

    The frequency response of a capacitor is mainly dependant on its
    dialectic and its package, not the capacitance. So there is no
    advantage in using a mixture of small capacitors - that idea is mainly a
    hangover from the old through-hole days when the packages were
    significantly different. As a rule of thumb, 100 nF caps work fine for
    bypassing - there is seldom need to go lower.

    As for the number you need, it depends on the type of components you
    use, their speeds and current requirements, and the quality of your
    power and ground routing. If you have good routing (power planes, or at
    least polygons and thick tracks), then you don't need as many - there is
    certainly no requirement for one cap per VCC pin. If your power routing
    is not so solid, add a few more capacitors, and scatter them around the

    In addition, you need bulk capacitors as part of your power supply,
    which are normally placed near the supply regulators or power
    connectors. If you have a lot of high power fast components (such as
    fpgas, or fast micros or memory), you might also want a few local bulk
    capacitors of around 10uF here and there to reduce the size of the
    low-frequency currents back to the power supply.

    But as other posters have said, everyone has their own theories. Unless
    you are talking about many hundreds of MHz, or very high resolution
    analogue, there is a great variety of methods for successful decoupling

  8. John  Larkin

    John Larkin Guest

    Why? The plate and contact geometry determine ESL, not the dielectric.

  9. I read in that John Larkin
    The dielectric determines the distance between terminations, for a given
    dielectric thickness set by mechanical strength issues, and that
    determines the inductance.
  10. John  Larkin

    John Larkin Guest

    In real life, there's hardly any difference in esl between caps of a
    given size. All 0805's are around 0.7 nH.

  11. I read in that John Larkin
    YES, that's because the inductance is determined by the distance between
    the terminations. One company now makes 0508 caps, with correspondingly
    lower inductance.
  12. Joerg

    Joerg Guest

    Hello David,
    That can be a recipe for trouble. Mostly in the form of purchasing guys
    running down the hallway towards your office because they can't get
    enough of the caps or the things went on allocation. If you max out the
    capacitance versus size factor at a given voltage the number of
    available manufacturers can shrink dramatically. Even down to one, and
    occasionally down to zero ...

    Regards, Joerg
  13. The OP was thinking about a system with clock frequencies up to 50
    MHz. In a 50 MHz square wave, there is a strong harmonic at 150 MHz.
    At 150 MHz, the 0.7 nH would represent a 0.7 ohm inductive reactance.

    A wire (or PCB track) would have an inductance about 1 nH/mm, thus the
    inductive reactance at 150 MHz would be 1 ohm/mm of PCB track.

    Since badly decoupled boards work after all, the chips must tolerate
    much larger voltage dips than specified :).

  14. John  Larkin

    John Larkin Guest

    Yes. The other thing that makes fast boards work is the capacitance
    between the pcb planes, which handle the fast stuff. The bypass caps
    just help out on the slower domains. On a decent multilayer board, it
    doesn't much matter where you put the bypass caps.

  15. Joerg

    Joerg Guest

    Hello Paul,
    They might until some day a glitch happens because this time bits 2, 4
    and 7 were flipping simultaneously which they usually don't ...

    Regards, Joerg
  16. David Brown

    David Brown Guest

    Perhaps I should have said "type of capacitor", rather than just the
    dielectric. In my (admittedly limited) understanding, the dielectric
    does affect the ESR, but that may be indirectly - with different
    dielectrics, the capacitor may be built physically differently (perhaps
    more or less compact vertically, for instance). I think ESL is
    dominated by the leads and connections (which also affect ESR).

    Either way, when doing high speed decoupling, you'll want to look at
    capacitors with lower ESR and ESL. You might decide it is cheaper and
    easier with several more standard capacitors, but it is certainly
    something to think about.
  17. David Brown

    David Brown Guest

    That's always important (and often underestimated by developers...).
    But that's why I wrote "in your voltage, price and *availability* range" :)


  18. Joerg

    Joerg Guest

    Hello David,
    Yes, then you should be fine. But the availability range can change
    suddenly and without notice. Remember the days when those small Z5U were
    all the rage and suddenly this ceramic material became scarce? I forgot
    the details but IIRC a chemical plant in Asia went kablouie. The guys
    that had settled for the larger X7R caps could continue to sleep at night.

    Regards, Joerg
  19. Joerg

    Joerg Guest

    Hello David,
    What mostly determines the quality of decoupling is placement strategy
    and traces to the chip pins. I have seen boards where they had a nice
    cap next to each chip but then ran a teeny trace to the pin, whatever
    the default of the layout program was.

    Regards, Joerg
  20. Even if you get the cap up close to the pin, and connected with a
    trace as wide as the capacitor, you still need a low inductance via to
    the power layer. I think it is a good idea to use two vias, one on
    each side of the cap pad (as close as is allowed) and angled a bit
    toward the other end, to get the best use of the capacitor.
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