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Debouncing....at About 1Mhz

Discussion in 'Electronic Design' started by D from BC, Nov 1, 2007.

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  1. D from BC

    D from BC Guest

    On Fri, 02 Nov 2007 20:26:21 -0700, John Larkin

    [snip]
    All fortune cookies are so positively biased.

    What if people got these in fortune cookies :)

    "Leave a big tip for extra luck"
    "Please check another fortune cookie"
    "Game piece 27...Get all pieces and win a free fortune cookie"
    "Only 21 calories!"
    "For success, do not read this fortune cookie"
    "Fortune cookie business for sale. Only $44000. Call ***.***"
    "Get 2x larger see www.bazookapenis.com"
    "You've opened our 1millionth fortune cookie!"
    "Medium size. Wash in luck warm water. No ironing."


    D from BC
     
  2. John Larkin

    John Larkin Guest

    Well, there's 4 prop delays from the falling edge input to the output.

    And not to be *too* critical, but this is a classic hazard-filled
    spaghetti-code glitch-driven asynchronous mess. For example, a fast
    glitch can fire both flipflops. And the circuit has four internal
    states, one of which is a hangup state, with both flops set; it will
    probably manage to find its way into that situation, and can never get
    out.

    My circuit is better because it has no unnecessary states, and because
    it's simple and easy to understand. Much faster, too. The
    lowpass+schmitt is even better if you can tolerate the delay.

    Asynchronous circuits are inherently hazardous, and desperately *want*
    to screw up, so should be kept as simple as possible.

    John
     
  3. D from BC

    D from BC Guest


    Here's what I've finally coughed up... :O *

    http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg
    547Kb slightly crappy LTSpice screen capture

    Notes
    ------
    * Circuit not reduced yet...
    * RC values, gate prop, generators will all be adjusted later for
    proper timing.
    * I chose this timing just to use the default gate parameter
    settings..(laziness).
    * 1st time doing so much digital in LTSpice... (Most of my digital is
    done in CM2000)


    Circuit Description
    -------------------
    D latch A2 latches on 1st positive edge
    D latch A1 latches on 1st negative edge

    Each latch triggers a one-shot circuit which resets the neighboring
    latch.
    Each one shot period is just slightly longer than the bounce period.


    It looks like it works...

    Open to comments or feedback...

    D from BC
     
  4. John Larkin

    John Larkin Guest


    No, it needs to be simpler.

    I know guys who would say "gee, I can add a hang-state detector that
    senses when both flipflops are set for some time interval, then resets
    both of them."

    John
     
  5. D from BC

    D from BC Guest

    I've noticed the IE seems to butcher this image at my end...I suspect
    image resize distortion.
    When I view the file using windows picture viewer, the image looks
    fine.
    Viewing might be better on a webpage
    http://www.members.shaw.ca/chainsaw/SED


    D from BC
     
  6. D from BC

    D from BC Guest

    Brutal! :)

    Yup... I now see that 4 prop delay from the falling edge input to the
    output.
    Darn..

    My spaghetti needs a bandaid. :)


    D from BC
     
  7. whit3rd

    whit3rd Guest

    [where edge A is low-to-high and B is high-to-low]

    So, use a nonretriggerable monostable with rising clock to
    make a pulse at A, another with falling clock to make a pulse
    at B, and Set/Reset a flop flop with those. Use the monostable A
    output to gate (inhibit) the B trigger, and the B output to gate the
    A trigger. As long as the monostable time
    is set longer than the jitter window, you're golden.
    Well, the trigger/output propogation delay has to be shorter than
    the delay to first false transition...

    For retriggerable monostables, the extra edges will stretch the
    output pulse; if the stable time is guaranteed longer than the
    monostable period, that's OK too.

    The nonclassic solution is filtering followed by a Schmitt trigger.
    That introduces phase delay, of course, and senses some average
    over time rather than the initial edges.
     
  8. John Fields

    John Fields Guest

    ---
    It's not 'it's', it's 'its'.

    So, you were asking for something frivolously, disregarding the
    investment in time someone seriously interested in helping you would
    have to expend in order to meet your ~10ns "requirement", when that
    10ns spec was just there to make you look "cool" in your bosses'
    eyes?
    ---
    ---
    First you need to learn to walk.
    ---
    ---
    Don't you mean that you can ask someone to do an ultra fast version
    for you another day?

    Anyway, here's the simulation I promised you, in LTSPICE:

    Version 4
    SHEET 1 1924 1060
    WIRE -1040 -304 -1632 -304
    WIRE -944 -256 -976 -256
    WIRE -1040 -240 -1296 -240
    WIRE -416 -224 -448 -224
    WIRE -320 -224 -352 -224
    WIRE -224 -224 -320 -224
    WIRE -32 -224 -224 -224
    WIRE 96 -224 32 -224
    WIRE -1632 -208 -1632 -304
    WIRE -1600 -208 -1632 -208
    WIRE -1504 -208 -1536 -208
    WIRE -1408 -208 -1504 -208
    WIRE -1264 -208 -1408 -208
    WIRE -320 -192 -320 -224
    WIRE -32 -192 -112 -192
    WIRE -224 -176 -224 -224
    WIRE 208 -176 160 -176
    WIRE -1504 -160 -1504 -208
    WIRE -1152 -160 -1200 -160
    WIRE -1088 -160 -1152 -160
    WIRE -944 -160 -944 -256
    WIRE -912 -160 -944 -160
    WIRE 96 -160 64 -160
    WIRE -1408 -144 -1408 -208
    WIRE -1296 -144 -1296 -240
    WIRE -1264 -144 -1296 -144
    WIRE 208 -144 208 -176
    WIRE -1152 -128 -1152 -160
    WIRE 64 -128 64 -160
    WIRE -1296 -112 -1296 -144
    WIRE -800 -112 -848 -112
    WIRE -912 -96 -944 -96
    WIRE 64 -96 208 -144
    WIRE -1296 -80 -1152 -128
    WIRE 208 -80 64 -128
    WIRE -1152 -64 -1296 -112
    WIRE -320 -64 -320 -112
    WIRE -224 -64 -224 -112
    WIRE -224 -64 -320 -64
    WIRE 64 -64 64 -96
    WIRE 96 -64 64 -64
    WIRE -1296 -48 -1296 -80
    WIRE -1264 -48 -1296 -48
    WIRE 208 -48 208 -80
    WIRE 208 -48 160 -48
    WIRE -1152 -32 -1152 -64
    WIRE -1152 -32 -1200 -32
    WIRE -1504 -16 -1504 -80
    WIRE -1408 -16 -1408 -80
    WIRE -1408 -16 -1504 -16
    WIRE -1088 -16 -1088 -160
    WIRE -1040 -16 -1088 -16
    WIRE -224 -16 -224 -64
    WIRE -944 0 -944 -96
    WIRE -944 0 -976 0
    WIRE 96 0 64 0
    WIRE -1264 16 -1296 16
    WIRE -1040 48 -1088 48
    WIRE -1408 64 -1408 -16
    WIRE -800 96 -800 -112
    WIRE -736 96 -800 96
    WIRE -224 96 -224 64
    WIRE -32 96 -224 96
    WIRE 64 96 64 0
    WIRE 64 96 32 96
    WIRE 96 96 64 96
    WIRE 208 96 208 -48
    WIRE 208 96 176 96
    WIRE -1296 112 -1296 16
    WIRE -1264 112 -1296 112
    WIRE -1152 112 -1152 -32
    WIRE -1152 112 -1184 112
    WIRE -1296 128 -1296 112
    WIRE -640 144 -672 144
    WIRE -224 144 -224 96
    WIRE -736 160 -800 160
    WIRE -800 192 -800 160
    WIRE -640 192 -640 144
    WIRE -608 192 -640 192
    WIRE -1408 208 -1408 144
    WIRE -1296 208 -1296 192
    WIRE -1296 208 -1408 208
    WIRE -448 240 -448 -224
    WIRE -448 240 -544 240
    WIRE -1408 256 -1408 208
    WIRE -608 256 -640 256
    WIRE 208 272 208 96
    WIRE 208 272 -64 272
    WIRE 320 272 208 272
    WIRE -1632 304 -1632 -208
    WIRE -800 304 -800 256
    WIRE -800 304 -1632 304
    WIRE -736 304 -800 304
    WIRE -640 320 -640 256
    WIRE -640 320 -672 320
    WIRE 416 320 384 320
    WIRE 320 336 272 336
    WIRE -1632 352 -1632 304
    WIRE -1040 352 -1632 352
    WIRE 416 352 416 320
    WIRE -736 368 -800 368
    WIRE 272 368 272 336
    WIRE -944 400 -976 400
    WIRE 272 400 416 352
    WIRE -1040 416 -1152 416
    WIRE 416 416 272 368
    WIRE 272 432 272 400
    WIRE 320 432 272 432
    WIRE -1632 448 -1632 352
    WIRE -1600 448 -1632 448
    WIRE -1504 448 -1536 448
    WIRE -1408 448 -1504 448
    WIRE -1264 448 -1408 448
    WIRE 416 448 416 416
    WIRE 416 448 384 448
    WIRE 496 448 416 448
    WIRE -1152 496 -1152 416
    WIRE -1152 496 -1200 496
    WIRE -944 496 -944 400
    WIRE -912 496 -944 496
    WIRE -64 496 -64 272
    WIRE -16 496 -64 496
    WIRE 320 496 208 496
    WIRE -1264 512 -1296 512
    WIRE -800 512 -800 368
    WIRE -800 512 -848 512
    WIRE -1152 528 -1152 496
    WIRE -448 528 -448 240
    WIRE -416 528 -448 528
    WIRE -320 528 -352 528
    WIRE -224 528 -320 528
    WIRE -16 528 -224 528
    WIRE 96 528 48 528
    WIRE -1296 544 -1296 512
    WIRE -912 560 -944 560
    WIRE -1296 576 -1152 528
    WIRE 208 576 208 496
    WIRE 208 576 160 576
    WIRE -1152 592 -1296 544
    WIRE -112 592 -112 -192
    WIRE 64 592 -112 592
    WIRE 96 592 64 592
    WIRE -1632 608 -1632 448
    WIRE -1504 608 -1504 448
    WIRE -1408 608 -1408 448
    WIRE -1296 608 -1296 576
    WIRE -1264 608 -1296 608
    WIRE 208 608 208 576
    WIRE -1152 624 -1152 592
    WIRE -1152 624 -1200 624
    WIRE 64 624 64 592
    WIRE -1152 640 -1152 624
    WIRE -1040 640 -1152 640
    WIRE -944 656 -944 560
    WIRE -944 656 -976 656
    WIRE -320 656 -320 528
    WIRE -224 656 -224 528
    WIRE 64 656 208 608
    WIRE -1264 672 -1296 672
    WIRE 208 672 64 624
    WIRE 64 688 64 656
    WIRE 96 688 64 688
    WIRE -1088 704 -1088 48
    WIRE -1040 704 -1088 704
    WIRE 208 704 208 672
    WIRE 208 704 160 704
    WIRE -1088 752 -1088 704
    WIRE 96 752 64 752
    WIRE -1296 768 -1296 672
    WIRE -1264 768 -1296 768
    WIRE -1152 768 -1152 640
    WIRE -1152 768 -1184 768
    WIRE -1296 784 -1296 768
    WIRE -320 848 -320 736
    WIRE -224 848 -224 720
    WIRE -224 848 -320 848
    WIRE -32 848 -224 848
    WIRE 64 848 64 752
    WIRE 64 848 32 848
    WIRE 96 848 64 848
    WIRE 208 848 208 704
    WIRE 208 848 176 848
    WIRE -1632 864 -1632 688
    WIRE -1504 864 -1504 688
    WIRE -1504 864 -1632 864
    WIRE -1408 864 -1408 672
    WIRE -1408 864 -1504 864
    WIRE -1296 864 -1296 848
    WIRE -1296 864 -1408 864
    WIRE -1088 864 -1088 832
    WIRE -1088 864 -1296 864
    WIRE -1632 928 -1632 864
    WIRE -320 928 -320 848
    FLAG -1632 928 0
    FLAG -1408 256 0
    FLAG -224 144 0
    FLAG -320 928 0
    SYMBOL res -1168 752 R90
    WINDOW 0 -13 53 VBottom 0
    WINDOW 3 39 54 VTop 0
    SYMATTR InstName R6
    SYMATTR Value 100k
    SYMBOL cap -1312 784 R0
    WINDOW 0 -38 31 Left 0
    WINDOW 3 -56 56 Left 0
    SYMATTR InstName C4
    SYMATTR Value 1e-7
    SYMBOL Digital\\or -1232 416 R0
    WINDOW 0 3 107 Left 0
    SYMATTR InstName A12
    SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\or -1232 704 M180
    WINDOW 0 -1 114 Left 0
    SYMATTR InstName A13
    SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL voltage -1632 592 R0
    WINDOW 0 -53 5 Left 0
    WINDOW 3 -242 110 Invisible 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V4
    SYMATTR Value PULSE(0 5 0 1E-6 1E-6 .1 .25)
    SYMBOL cap -1536 432 R90
    WINDOW 0 -30 32 VBottom 0
    WINDOW 3 -28 35 VTop 0
    SYMATTR InstName C5
    SYMATTR Value 1e-7
    SYMBOL res -1520 592 R0
    SYMATTR InstName R7
    SYMATTR Value 10k
    SYMBOL diode -1392 672 R180
    WINDOW 0 -39 33 Left 0
    WINDOW 3 -75 -2 Left 0
    SYMATTR InstName D2
    SYMATTR Value 1N4148
    SYMBOL Digital\\and -1008 320 R0
    SYMATTR InstName A14
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL voltage -1088 736 R0
    WINDOW 0 28 15 Left 0
    WINDOW 3 -242 110 Invisible 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V5
    SYMATTR Value PULSE(0 5 0 1E-6 1E-6 .5e-3 1e-3)
    SYMBOL Digital\\and -1008 736 M180
    SYMATTR InstName A15
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -880 592 M180
    SYMATTR InstName A16
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL res -1168 96 R90
    WINDOW 0 -12 56 VBottom 0
    WINDOW 3 39 54 VTop 0
    SYMATTR InstName R4
    SYMATTR Value 100k
    SYMBOL cap -1312 128 R0
    WINDOW 0 -38 31 Left 0
    WINDOW 3 -56 56 Left 0
    SYMATTR InstName C1
    SYMATTR Value 1e-7
    SYMBOL cap -1536 -224 R90
    WINDOW 0 -30 32 VBottom 0
    WINDOW 3 -28 35 VTop 0
    SYMATTR InstName C6
    SYMATTR Value 1e-7
    SYMBOL res -1520 -176 R0
    SYMATTR InstName R5
    SYMATTR Value 10k
    SYMBOL diode -1424 -144 R0
    SYMATTR InstName D3
    SYMATTR Value 1N4148
    SYMBOL Digital\\and -1008 -336 R0
    SYMATTR InstName A7
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -1008 80 M180
    SYMATTR InstName A8
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -880 -192 R0
    SYMATTR InstName A18
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -1232 -240 R0
    SYMATTR InstName A19
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -1232 48 M180
    SYMATTR InstName A20
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL voltage -1408 48 R0
    WINDOW 0 28 15 Left 0
    WINDOW 3 -242 110 Invisible 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V6
    SYMATTR Value 5
    SYMBOL Digital\\and -704 64 R0
    SYMATTR InstName A5
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -704 400 M180
    SYMATTR InstName A6
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and -576 160 R0
    SYMATTR InstName A9
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\inv -864 256 R270
    SYMATTR InstName A10
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and 352 240 R0
    SYMATTR InstName A1
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and 352 528 M180
    SYMATTR InstName A4
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL res 192 80 R90
    WINDOW 0 -14 59 VBottom 0
    WINDOW 3 39 54 VTop 0
    SYMATTR InstName R9
    SYMATTR Value 100k
    SYMBOL cap 32 80 R90
    WINDOW 0 0 32 VBottom 0
    WINDOW 3 32 32 VTop 0
    SYMATTR InstName C9
    SYMATTR Value 2e-7
    SYMBOL cap -352 -240 R90
    WINDOW 0 -30 32 VBottom 0
    WINDOW 3 -28 35 VTop 0
    SYMATTR InstName C10
    SYMATTR Value 1e-8
    SYMBOL res -336 -208 R0
    SYMATTR InstName R10
    SYMATTR Value 10k
    SYMBOL diode -240 -176 R0
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL Digital\\and 128 -256 R0
    SYMATTR InstName A25
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\and 128 32 M180
    SYMATTR InstName A26
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL voltage -224 -32 R0
    WINDOW 0 28 15 Left 0
    WINDOW 3 -242 110 Invisible 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value 5
    SYMBOL res 192 832 R90
    WINDOW 0 -15 59 VBottom 0
    WINDOW 3 39 54 VTop 0
    SYMATTR InstName R11
    SYMATTR Value 100k
    SYMBOL cap 32 832 R90
    WINDOW 0 0 32 VBottom 0
    WINDOW 3 32 32 VTop 0
    SYMATTR InstName C11
    SYMATTR Value 2e-7
    SYMBOL Digital\\or 128 496 R0
    WINDOW 0 3 107 Left 0
    SYMATTR InstName A27
    SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\or 128 784 M180
    WINDOW 0 -1 114 Left 0
    SYMATTR InstName A28
    SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL cap -352 512 R90
    WINDOW 0 -30 32 VBottom 0
    WINDOW 3 -28 35 VTop 0
    SYMATTR InstName C12
    SYMATTR Value 1e-8
    SYMBOL res -336 640 R0
    SYMATTR InstName R12
    SYMATTR Value 10k
    SYMBOL diode -208 720 R180
    WINDOW 0 -39 33 Left 0
    WINDOW 3 -75 -2 Left 0
    SYMATTR InstName D6
    SYMATTR Value 1N4148
    SYMBOL Digital\\and 16 576 M180
    SYMATTR InstName A29
    SYMATTR Value2 trise 1e-6 tfall 1e-6 vhigh 5v
    SYMBOL Digital\\or 0 -272 R0
    WINDOW 0 3 107 Left 0
    SYMATTR InstName A30
    SYMATTR SpiceLine trise 1e-6 tfall 1e-6 vhigh 5v
    TEXT -1608 896 Left 0 !.tran .5
    TEXT -1344 -376 Left 0 ;SIGNAL GENERATOR
    TEXT -184 -376 Left 0 ;DEBOUNCER
    TEXT 512 448 Left 0 ;OUTPUT

    The concept is there, and it works, so all you need to do is convert
    the circuit to a TTL equivalency, if that's what you want to use,
    and maybe use some diodes instead of gates to get the chip count
    down.

    You know how to do that, right?

    Larkin's down to two chips, but he's got a lot of RFI going on since
    every transition of the input signal generates spikes all through
    his delay network and into the air.
     
  9. D from BC

    D from BC Guest

    Actually.. I've been neglecting to watch out for a freeze up problem.

    I had another bandaid in mind..

    The bandaid was adding 2 NAND gates and a SR to my cct on
    http://www.members.shaw.ca/chainsaw/SED/DfromBCdebounce.jpg

    I think I just reinvented John Fields circuit (The circuit with the 2
    one shots.)

    Ok.....I'm going to look at your circuit.
    As on..
    http://s2.supload.com/free/Deglitch.JPG/view/


    D from BC
     
  10. John Larkin

    John Larkin Guest


    Hairball.

    John
     
  11. John Larkin

    John Larkin Guest

    That makes it even more complex, and adds new hazards.

    It's extremely difficult, or more likely impossible, to prove that a
    mess like this is safe. That's why asynchronous logic is seldom used
    where it really matters.

    A synchronous state machine can be proven to be correct. And it can
    have hang states that are not a hazard because it can be proved that
    they can never be entered. An async machine like this one will be
    teased billions of times in its lifetime, and if it has a chance of
    hanging, it probably will.
    You'll never prove that it's safe. It way too complex, and way to
    slow, anyhow.
    As has been pointed out a few times, it inverts. So take the output
    from Qbar.

    I'd still go for the lowpass-schmitt.


    John
     
  12. D from BC

    D from BC Guest

    On Sat, 03 Nov 2007 20:00:00 -0500, John Fields

    [snip]
    ok ...ok..
    I guess it's (correct use of apostrophe) not cool to back off on a
    spec after some time..
    I should have included in the 1st post some dream specs, some lower
    and upper specs.
    I do have a real justified technical reason for needing minimal edge
    to edge delay. Not just for sport...
    And I do plan on building a debounce circuit this month.

    I was trying to make this point....
    If the circuit problem is too heavy then I'll settle for simpler
    longer prop. time designs.
    Those would be quicker to post and describe. Also, those designs can
    be an inspiration to faster designs.

    Yup... I've done some DTL circuits to reduce chips.

    About your circuit.....

    Holy frick batman! :O
    What amount should I put on the check? :)

    You did the generator too!

    I cheated on that ... :p
    http://www.members.shaw.ca/chainsaw/SED
    2 sine generators and a comparator.

    Huh...I didn't know the unused pins could be left open in LTSpice...I
    guess I should read the whole manual someday...It was driving me nuts
    to hook up all the unused inputs.

    Heyy! This is a fun problem :)
    I've got papers all over the floor from trying to figure this out on
    my own..

    k...I'm gonna take this circuit for a test drive... :)

    Thanks. :)

    More later...
    D from BC
     
  13. John Larkin

    John Larkin Guest

    You can never prove that a thing like that works right. Which means
    that it probably doesn't.
    Hairball.

    John
     
  14. D from BC

    D from BC Guest

    It seems to be the trend.
    I realized some of those monostable requirements when I tried to solve
    the circuit.
    Also, I suspect John Fields ascii circuit and posted LTspice file use
    similar approaches.
    One channel for the positive edge processing. A timing action.
    One channel for the negative edge processing. A timing action.
    Some cross resetting and final decoding..

    The sequence is something like this.

    Trigger on positive edge.
    Let fuzz pass by.
    Clear negative edge in preparation for 1st incoming negative edge.
    Trigger on negative edge.
    Let fuzz pass by.
    Clear positive edge in preparation for incoming positive edge.

    The pita part is attempting low prop delay for 1st pos edge and 1st
    neg edge.
    The SN74LV123A retrig MM has a tpd of [email protected] at the top of the
    datasheet.
    D from BC
     
  15. D from BC

    D from BC Guest

    On Sat, 03 Nov 2007 19:45:01 -0700, John Larkin

    [snip]
    Oh come on... I think JFs (apostrophe used correctly?) has a logical
    progression with low propagation in mind.

    If I understand it correctly..

    It's got edge extraction.
    It's got 2 parallel paths per edge type.
    And 2 timers to knock out the fuzz.

    I'm guessing the required shopping list for this type of circuit is :

    A means to detect the 1st positive edge.
    A means to detect the 1st negative edge.
    An ignore timer for the fuzz after the 1st positive edge.
    An ignore timer for the fuzz after the 1st negative edge.


    D from BC
     
  16. D from BC

    D from BC Guest

    I'm checking out how the Deglitch cct behaves when the frequency is
    varied..

    (I forgot to mention in my first post that the frequency can vary but
    not the bounce period.)

    The hairball circuits can react to varying pulse widths and have a
    large operational BW.


    D from BC
     
  17. Fred Bloggs

    Fred Bloggs Guest

    It would be simpler to learn how to terminate your signals properly...
     
  18. John Fields

    John Fields Guest

    ---
    Nope, apostrophes are used to form possessive of nouns, so it should
    be "JF's". :)

    http://owl.english.purdue.edu/handouts/grammar/g_apost.html
    ---
    ---
    Yup. The positive edge processing is 5 gate delays from input to
    output and the negative edge is 3. There's probably some
    optimization that can be done, but I was just looking to prove the
    validity of the concept.
    ---

    ---
    Yes, but the timer is to keep the fuzz from firing the _other_
    circuit once the first edge fires its own circuit.

    Don't mind Larkin, he generally pooh-poohs everything that doesn't
    come out of his shop. NIH, it's called. ;)
     
  19. John Fields

    John Fields Guest

     
  20. John Fields

    John Fields Guest

     
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