Discussion in 'Electronic Design' started by D from BC, Nov 1, 2007.

1. ### D from BCGuest

This has got to be a classic signal clean up problem....

I need a circuit that triggers on edge A, then ignores about 0.1uS of
jitter then triggers on edge B and then ignores a following 0.1uS of
jitter.

+-+ +-+ +----------------+ +-+ +-+
In | | | | | | | | | |
A | | | | B | | | |
-------+ +-+ +-+ +-+ +-+ +-----------

|<0.1uS>| |<0.1uS >|
|< 0.5uS >|

Out +------------------------+
| |
A' B'
-------+ +-------------

Edge A to A' is ~ less than 10nS
Edge B to B' is ~ less than 10nS

All values are approximates.
"In" and "Out" are repeating waveforms.

I think I can do it with:

1 flip flop
1 >0.1us delay circuit
Sprinkled with gates..

Or maybe I need 2 flip flops..one for edge A and one for edge B..

I'm not even sure yet which type of FF to get.

If anybody has done this problem before and doesn't mind sharing..let
me know a topology...

In the meantime, I'll be doodling until I get a solution...

D from BC

2. ### WinfieldGuest

Are you sure the word you want is "jitter"? Once an edge
is detected, there's nothing until the corresponding next
opposite edge, right? The word jitter describes a periodic
time uncertainty for when an edge will arrive, not what
happens immediately after the edge arrives. If in fact
in the 100ns after an edge, that's not called jitter.
It's a type of digital noise.

Anyway, if you add an XOR gate to your mix of available
pieces, you'll be able to find a simple solution allowing
the use of only a single oneshot delay element. But I
might point out that most oneshot ICs come as dual parts.
You may get a lower chip count by using two timers. BTW,
there's a simple way to adjust the delay of two oneshots
with one trimpot or external panel pot. It could even be
a 10-turn precision pot with a turns-counting dial.

3. ### Fred BloggsGuest

It would be simpler to learn how to terminate your signals properly.

4. ### John LarkinGuest

Looks like you can do it with a dflop, a quad xor, and an RC.

Run the input through a delay-line edge detector (three gates of
delay, then xor) and clock the dflop. Then rc lowpass the input and
apply it to D. Q is the output.

John

5. ### D from BCGuest

Yeah...jitter is probably the wrong word..
I thought of jitter as some interval of spurious digital behavior.
http://en.wikipedia.org/wiki/Jitter

One shots ICs and xors...neato!
I've haven't thought about that yet.
I'll give it a shot (<<pun!).

I'll post a link to schematic variations once I settle on a design.

D from BC

6. ### D from BCGuest

Are you thinking reflection?

The source signal is from pcb power section with high di/dt and dv/dt.

D from BC

7. ### RST Engineering \(jw\)Guest

Seems to me that you could do it with a D flop, and two RC nets from Q to R
and /Q to S to hard-hold it high or low for a tenth of a usec.

Jim

8. ### D from BCGuest

Ahhhhh...........

I'll try drawing it while stuck in traffic...

Thanks..

D from BC

10. ### John FieldsGuest

---
I think this'll work, conceptually, but to get that <10ns in-out
delay (especially considering the propagation delay through the
one-shot)you'll probably need to go ECL since even FAST is iffy.

View in Courier:

___
SET
IN>-+-----------------A /
| NAND Y------A
+-[250ns]--+------B NAND Y--+-->OUT
| \ / \ +--B |
| \ / DLY1 | |
| / | A--+
| / \ DLY2 +--Y NAND
| / \ / B--+
+-[250ns]--+------A |
| OR Y------------+
+-----------------B \___
RST

The blocks labeled '250ns are cross-coupled one-shots, the top one
high-going edge triggered and the bottom one low-going edge
triggered. When either one is hot it keeps the other one from
triggering on the bounce transitions after the first edge.

Here's the timing:

_ _ _ _ ___________ _ _____ _ _ _ _
IN___|_|_|_|_| |_|_|_|_|___________

______________
DLY1__| |___ _ _________________________

___ ___ __ _ _________________________
SET |______________|

____ ____________________ _ ______ ___
DLY2 |______________|

___ _____________________ _ _______ __
RST |______________|

________________ _ ________
OUT ____| |________________

I'm working out a simulation in LTSPICE, and it should be ready
sometime tomorrow.

John

13. ### Tom BruhnsGuest

Right, so the xor plus the dflop clock to output needs to have less
delay than that... should be easy with fast parts. The xor is just to
get the same polarity clock pulse from each (leading) clock edge. The
d input is RC delayed, so you capture the "old" level; thus you take Q-
not as the output. RC must be long enough to get past the multiple
transitions at each edge. In fact, you could do it, I think, with an
SR f/f (cross-coupled NANDs) driven from a similar xor nanded with RC-
filtered clock...

Cheers,
Tom

14. ### John FieldsGuest

---
It's about equivalent to "Huh???", basically questioning whether
your scheme could get a clean, debounced output less than 10
nanoseconds after the input edge, which was one of the OP's
requirements.

Especially since, with that quad EXOR, you seem to be talking
TTLish.

17. ### John FieldsGuest

---
No, the clock input is nominally high, so when a new edge comes
along it'll drive the clock input low. Then, after _three_ EXOR
gate delays it'll clock whatever's on D to Q, so the input-to-output
delay will be three EXORs plus one dflop.

BTW, what CMOS parts did you have in mind?

It is not.

0 xor 0 = 0

1 xor 1 = 0

John

19. ### D from BCGuest

oh nooo.. I rushed another post and again left out details...

Ton can vary up to 0.5uS..
(Ton is the 0.5uS time in my ascii drawing.)
The circuit should at least function between 100khz and 1Mhz.
The only thing that is constant is the bounce time of about 0.1uS.

Was that one shot idea based on constant Ton? Or variable Ton?

D from BC

20. ### D from BCGuest

Ideally..edge A is transparent through the circuit.
Ideally. edge B is transparent through the circuit.
But no no no...everything takes time and I have to allow a max delay.

I have a timing budget of around 10nS for A to A' and B to B'.
This circuit is being inserted in a chain . All the delays are adding
up..
10nS is tolerable and at first guess seems attainable.

By the way.. I just made up the A and A' nomenclature...
Reserved?
I do try to express problems in some way to be clear and simple.

D from BC