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DDR SDRAM static timing analysis

Discussion in 'Electronic Design' started by [email protected], Oct 13, 2006.

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  1. Guest

    I need a help in static timing analysis for DDR interface to network
    processor . Processor say that its timing is as per JEDEC standard.

    For Read i will be use
    tSD (avg.) = (tDQSQ + tDV) ÷ 2
    and able to find the setup margin and the hold margin.

    But in the Write i am not able to calculate the same. Controller and
    DDR SDRAM say that it will provide/need 0.45 ns setup and hold time. I
    donot have any margin in that case. Can you let me know how do the do
    timing analysis for the write cycle.

    Thanks and regards
  2. PeteS

    PeteS Guest

    Tell us:

    1. The exact processor
    2. The memory you are using
    3. The speed you desire to run at

    and then we might be able to help.

    I do know that write cycle timing is easier to meet than read for
    standard DDR memory.


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