Connect with us

DDR design needs a little help

Discussion in 'Beginner Electronics' started by DanK, Jan 4, 2006.

Scroll to continue with content
  1. DanK

    DanK Guest

    Hopefully some nice DDR guru is out there...

    My DDR design is for a single REGISTERED DDR modules (64 bits wide plus
    ECC/parity bits). The module was acting like cas latency was 2.5 when I had
    set it to 2, so I changed my design to work with CL=2.5 and continued with
    the de-bug. Now I'm pretty sure the module thinks the burst length is set
    to 4, even though I set it to 2. (a 128 bit write to address 0/1 also gets
    written into address 2/3). I've gone over the initialization and I can't
    find anything wrong. Anybody got any ideas?


  2. PeteS

    PeteS Guest

    You don't say whether you are using someone else's DDR controller or
    are making your own.

    There are many adjustable parameters in a typical DDR controller (and
    in the DDR device - there are two accessible registers - status and
    extended status).

    Apart from the multiple writes, what other issues (faults) do you see?


  3. DanK

    DanK Guest

    Its my own controller in an fpga and it definatly thinks burst length = 4 as
    I see a double DSQ pulse on a read. A 1GB modue works correctly, the 2 GB
    module does not (both work in a server motherboard so I know the ddr is
    good). Other than the multiple writes everything seems to work.
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day