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DAC specifications

J

john

Jan 1, 1970
0
Hello All,

I have chosen analog devices AD5532HS for my project. The main reason
that I chose this DAC was because of its 32 voltage output channels.
You can find the DAC at
http://www.analog.com/static/imported-files/data_sheets/AD5532HS.pdf


My post is long and I request you to be patience and helpful. I need
your help to understand and finalize the following issues


1. The data sheet says that the DAC has the update rate of 1.1MHz.
So,
the update rate for 32 channels will be (1.1M) / 32 = 34 KHz per
channel. Am I right?


2. The output waveform at each channel should consist of 32
digital
samples. The DAC requires 30MHz (33.3 nsec) of serial clock and 14
bit
of data and 5 bit of address bits to chose the channel. So, the DAC
requires 19 bit of data to update one of its 32 channel.


So, the total time required to input the 19 bits ( One Sample ) will
be (19 x 33.3 nsec) + 280nsec = 913.27 nsec (1MHz), Am I right?
913.27nsec x 32 = 29.22usec or 34 KHz. What will be the total
output rate of the DAC? (19 Mbps!!)


So, I send 19 bits of data 32 times to channel 0 to produce an analog
voltage waveform consists of 32 samples and then send the 19 bit data
to channel 1 and so on… Now,


a) How can I calculate the update delay rate between two consecutive
channels and channel 0 and channel 31?
b) What is the highest frequency waveform can I get from each channel
of the DAC, if I am trying to update all of them?


3. I tried to calculate THD for this DAC using THD % = (1/ 2^n) x
100. I chose 14 bit, so THD = 0.006 %.
What does this number really means. Is it good or bad? How can I
interpret the result?


4. Dynamic Range = (6.02 x n) + 1.76 = 86.4.
What does this number really means. Is it good or bad? How can I
interpret the result? And what is dynamic range?


5. This DAC has an ideal step size of 5 / 2^14 = 300uV = 1 LSB. Now,
the data sheet says that the offset error is 50mVolts, Does it mean
50mv = 49 bit error. Am I right? How can I convert the 50mV error
into
equivalent bit error? Is this error be permanent?


6. In order to calculate the accuracy of the DAC with my application,
I chose that +/- 4 LSB errors is tolerable, so the accuracy came out
to be


Accuracy = 14 – log2 (4) = 12
bits.


+/- 4 LSB = 0.0012 volts. Is this a right way to calculate the
accuracy of the system? I meant that what if I chose the error to be
+/- 2 LSB. How should I choose the allowable error for this DAC? How
can I make the output comes out of this DAC as accurate as possible?


Regards,
John
 
J

Jasen Betts

Jan 1, 1970
0
7On 2008-12-05 said:
Hello All,

I have chosen analog devices AD5532HS for my project. The main reason
that I chose this DAC was because of its 32 voltage output channels.
You can find the DAC at
http://www.analog.com/static/imported-files/data_sheets/AD5532HS.pdf
My post is long and I request you to be patience and helpful. I need
your help to understand and finalize the following issues


1. The data sheet says that the DAC has the update rate of 1.1MHz.
So,
the update rate for 32 channels will be (1.1M) / 32 = 34 KHz per
channel. Am I right?

within 5%

2. The output waveform at each channel should consist of 32
digital
samples. The DAC requires 30MHz (33.3 nsec) of serial clock and 14
bit
of data and 5 bit of address bits to chose the channel. So, the DAC
requires 19 bit of data to update one of its 32 channel.


So, the total time required to input the 19 bits ( One Sample ) will
be (19 x 33.3 nsec) + 280nsec = 913.27 nsec (1MHz), Am I right?
913.27nsec x 32 = 29.22usec or 34 KHz. What will be the total
output rate of the DAC? (19 Mbps!!)


So, I send 19 bits of data 32 times to channel 0 to produce an analog
voltage waveform consists of 32 samples and then send the 19 bit data
to channel 1 and so on…

no. 19 bits for channel 0, 19 bits for channel 1, and so on.
repeat 32 times.
a) How can I calculate the update delay rate between two consecutive
channels and channel 0 and channel 31?

(19 x 33.3 nsec) + 280nsec

((19 x 33.3 nsec) + 280nsec) *31
b) What is the highest frequency waveform can I get from each channel
of the DAC, if I am trying to update all of them?

nyquist says 0.5/ 29.22
3. I tried to calculate THD for this DAC using THD % = (1/ 2^n) x
100. I chose 14 bit, so THD = 0.006 %.
What does this number really means. Is it good or bad? How can I
interpret the result?

In context, there's no other way.
4. Dynamic Range = (6.02 x n) + 1.76 = 86.4.
What does this number really means. Is it good or bad? How can I
interpret the result? And what is dynamic range?
loudest/quietest

5. This DAC has an ideal step size of 5 / 2^14 = 300uV = 1 LSB. Now,
the data sheet says that the offset error is 50mVolts, Does it mean
50mv = 49 bit error. Am I right? How can I convert the 50mV error
into
equivalent bit error? Is this error be permanent?

semi-permanent I think. (slowly varying)
6. In order to calculate the accuracy of the DAC with my application,
I chose that +/- 4 LSB errors is tolerable, so the accuracy came out
to be


Accuracy = 14 – log2 (4) = 12
bits.


+/- 4 LSB = 0.0012 volts. Is this a right way to calculate the
accuracy of the system? I meant that what if I chose the error to be
+/- 2 LSB. How should I choose the allowable error for this DAC? How
can I make the output comes out of this DAC as accurate as possible?

not sure.
 

neon

Oct 21, 2006
1,325
Joined
Oct 21, 2006
Messages
1,325
you state update rate of 1.1mhz for 32 bits A/D your ref. better be 100 volts. this is a wannabe try. it could be that i miss understand you.
 
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