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D-flipflop Phase detectors - outputs of Qb and Qa?

Discussion in 'Electronic Basics' started by [email protected], Mar 5, 2006.

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  1. Guest

    If my phase detector for PLL is D-flipflop with Reset, what what the
    output be when the input B is lagging input A (reference) by 180 to 360

    Assume the inputs have same on time (e.g. 5ns) and same period (e.g.
    10ns) and the unput A is leading input B by 7.5ns (270 degrees). Should
    the output Qa stay on until the output Qb goes on, or should it go off
    after 5ns and then go on after another 5ns, so both outputs would be

  2. David Harmon

    David Harmon Guest

    On 5 Mar 2006 11:15:04 -0800 in sci.electronics.basics,
    Do not post copies of your question in multiple newsgroups.
    Pick one.
  3. Jamie

    Jamie Guest

    i think it should be no pulse output and if its
    designed like think it is ? you will only
    get a pulse output when one freq is just behind
    the other! other wise no pulse at all!
    this makes sure that correction is performed
    only in one direction.
    this is the same logic used when taking the
    A and B output from an incremental encoder to detect
    direction of rotation!, one way will generate a pulse
    and the other direction will generation no pulses.
    the pulse that is generated is the time width of
    when A and B happen to be one at the same time which is
    usually 25% duty cycle .
    in the case of PLL's this duty cycle varies depending on
    how far out of lock it is.
  4. Vitaliy

    Vitaliy Guest

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