Custom I2C bus concept, would it work?

In lieu of creating a mixed voltage bus (I.E. 5v to 12v to 5v) I'm considering an Open-Collector bus topology of higher current. Sinking higher current with transistors instead of chips allows the bus distance to be extended past standard distance.

Not a perfect method for a longer distance bus but seemingly possible.

Here is my design in theory:



The idealize transmission line in the center does have some resemblance to my application.

The PNP transistors sink most of the bus current while still passing a signal to devices and the zener diodes provide signal clamping.

Using some idealized simulations of these transistors and transmission line I have determined some details.

During the high to low transitions there is a ~50mA current spike through a PNP transistor with a fall time of around 150ns (~5V to 0V) but 500ns to settle at ~930mV given the simulated transmission line.

The low to high rise time is around 400ns (~930mV to 3.6V) with the same transmission line.

These rise and fall times are well within spec for the NXP PCA9634D IC I’m looking to use.

My question is, am I crazy? Do I have a valid theory? Are there any issues I'm overlooking?

I have minimum practical experience with serial transmission lines like this, especially one like this that doesn't follow I2C Spec.

Thanks for reading,

Reactor89

 

Of course.

I want to make an I2C bus of 18 devices on a 20ft long bus cable without a repeaters or bridges. (using repeaters is a last resort)

Capacitive load will be higher then the standard maximum (400pF). It's hard to say exactly how high but less than 1000pF.

I don't think shielded cable solves my issues. Such a large single bus is highly capacitive and is likely to first fail do to rise and fall time issues before noise.

To drive such a high capacitive load means running higher bus current to maintain the standard 100kHz I2C clock speed or maintaining standard current levels and customize I2C code to run the bus at a far lower clock frequency.

In either case I would be using a somewhat modified I2C standard to drive the extra long bus and I'm in uncharted territory.

If I was to use something other then I2C I would need to find a replacement to my NXP PCA9634 chip.

Reactor89

 

Thank you voicing concern about the noise and how the higher current methods make a bus far more susceptible to noise. This didn't quite occur to me when designing this method.

With this in mind and considering the mobile nature of my application, expanding the device footprint and adding I2C repeaters is the responsible design choice.

With a chain of repeaters (per the NXP PCA9507 documention) I can cut my large bus into smaller chunks and make the system much more resistance to noise.

Space is expensive but I will trade it for system robustness at this point.

Thanks for the input,

Reactor89

 

Well fine then. Never back down.

Yet the reason why I'm nervous is every I2C "Low Level Input Voltage" I've seen is 0.3 *VCC (TTL standard) including the chips I want to network.

That is low level is 1.5v max with 5v.

Giving the design a once over again and optimizing the resistors the low level for the circuit will be 830mV - 730mV depending on resistor layout. Again the Vbe at work.



So now the all important question is; is ~700mV margin for noise enough given I want to use standard ribbon cable on a mobile application?

I guess a I will need to prototype like you say and consider the results on an oscilloscope.

I will update later,

Reactor89