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Current Rating Question

Discussion in 'Electronic Design' started by N. Thornton, Jan 25, 2004.

  1. N. Thornton

    N. Thornton Guest

    Hi


    I have some small power transistors controlling low voltage half wave
    rectified 50Hz, and need to pare the tr specs down as far as poss. But
    I'm getting into territory I'm not really clear on.

    The tr is ON 10% to 40% of the time. This duty cycle is not exceeded,
    and the frequency of ON states is 50Hz, its chopping 50Hz.

    The Trs deliver:
    max i 1.0A
    0.9A average during the ON times, so overall average is anything up to
    0.36A)
    dissipating 0.5w. average during the ON states, giving a max average
    diss of 0.2w.

    Now I know I can reign back on the tr power diss specs because of the
    low duty cycle, and use a 0.2w tr, but as the power is so low thats
    not really an issue. The real question is can I reign back on the
    current specs for the same reason? And how far? Ie what must the tr's
    current spec be?


    Thanks, NT
     
  2. That's not that easy to say. Many transistors specify a peak current
    rating in addition to a constant current rating. The peak current rating
    is often specified for a duration of 0.3ms. How much you need to derate
    that because of your longer pulse duration is dependent on the thermal
    mass of the transistor.

    If you operate the transistor that close to the "edge", your saturation
    voltage goes way up, and the losses with it. At the same time beta goes
    down.

    So in practice you may well find that you can't derate the current spec
    enough to make a real difference. I presume you want to save cost. I
    suspect that you have more chance of saving significant expense by
    choosing a transistor that is produced in very high volume.

    Your ratings are low enough to fall in the range of rather cheap mass
    produced transistors, such as the BC639. So what's left to save?
     
  3. Stefan Heinzmann wrote...
    300us? I haven't noticed the significance of that value. But in general
    I can state that for the region below 1 to 10ms, the peak power that can
    be safely absorbed goes up inversely by the square root of the time. This
    result comes from the diffusion of heat through thermal masses surrounding
    the junction. For example, 10x more power can be handled in 3us compared
    to 300us. Using the P = I^2 R relationship, this means the BJT saturation
    current [or the Rds(on) current in the case of FETs] can be 1.8x higher for
    a 10x shorter time, or 3.3x higher for a 100x shorter time.

    By comparison, linear circuits (typically with pre-determined fixed voltage
    drops) benefit by a 3.3x per decade current increase with inverse time.

    Thanks,
    - Win

    whill_at_picovolt-dot-com
     
  4. I don't know whether it has any special significance, but I've
    encountered it quite often in data sheets. It coincides with the
    capabilities of the old industry standard curve tracer Tektronix 576,
    but I don't know whether chicken or egg was first.
    Beyond 10ms, I assume that the total thermal mass comes into play. Is
    there anything quantitative that can be said in this case? In
    particular, can I infer the thermal mass from anything I can find in
    data sheets or is it something I need to find out through measurements?
     
  5. N. Thornton

    N. Thornton Guest

    Hi

    Thanks Win, and Stefan. I mistooked: the duty cycle is in fact 5% to
    20%, not 10% to 40%. So the ON duration is 1ms to 4ms out of every
    20ms.

    So with 20% duty cycle max I could derate it by root 0.2 = 0.45. So I
    need a 450mA tr to supply the 1A output, according to this. I also
    must consider a peak rating for 4ms.

    I want to trim because I have a row of them, its not just single
    channel.


    Thanks, NT
     
  6. Stefan Heinzmann wrote...
    Yes, most power MOSFETs have a Transient Thermal Impedance curve that
    details this. Basically it's a time plot going from local thermal-mass
    heat absorption (with the rule I stated above) to steady-state heat
    conduction, where you use the standard thermal-resistance calculations.

    Thanks,
    - Win

    whill_at_picovolt-dot-com
     
  7. Ok, but what are you trying to optimize, and why? I suspected that you
    have several, otherwise optimization would be pointless. Are you trying
    to save money by going to smaller transistors? Are you trying to save
    chip area (because you're designing a custom chip)?

    You may find that your power losses go up (because of higher Vce sat) if
    you reduce transistor current ratings. Also, you may find that due to
    lower beta you have to drive the base of the transistor harder. So you
    can't just optimize one factor without watching the effect on other factors.
     
  8. N. Thornton

    N. Thornton Guest

    I'm trying to minimise cost. If it goes well it may make it into a
    chip, so minimising silicon area is the real goal. But I'll be
    building a discrete version first.

    Yup.

    Thanks, NT
     
  9. R.Legg

    R.Legg Guest

    Minimize cost in the immediate intended physical configuration. It's
    the only chance to get to the "all goes well" stage.

    Leave integration until that decision is made and when economically
    justified.

    RL
     
  10. N. Thornton

    N. Thornton Guest


    Right, good point.

    I do still need to understand how the duty cycle affects silicon area
    though, to justify continuing with it at this point, and I've found my
    knowledge coming up short on that.


    Thanks, NT
     
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