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Have taken the liberty of bring in the test from another part of this
thread because there are things in it that I'd like to point out to the OP
and others who are reading along at this point:
[... a lot of correct math deleted up to this point by DNA ...]
BUT all of that ignores the fact that the LCL section in a CUK converter
forms a resonant section which messes up the sums. Now I don't know how it
really messes up the sums but you are forced to close the loop below that
resonance if you are dealing with the input or output current, and there's
probably some sampled filter thing going on too.
DNA
For those who want more reading on the subject: try to find Advances In
Switch-Mode Power Conversion by R. D. Middlebrook and Slobodan Cuk. It
was published by TeslaCo in 1983.
I can tell you how to figure out where the poles land from the L1, L2 and
C1. The math isn't that hard.
The statement about the gain cross over having to be below that point is
wrong if the controller is current mode.
I'm about to make one more attempt to explaining the third item but I
think DNA is being intentionally as thick as two wet planks.
If you find Mr. Cuks works, look in Vol 1 and 2 on page 381 to see his
amplitude and phase vs frequency plots. Remember he is measuring from the
distrubance of the switching time to the output of the converter.
[...]
Sigh, you're barking up the wrong tree.
No, its you who's got the wrong end of this stick.
[..]
I'm going to try once more and then give up.
If you have a system, a portion of which is sampled, that you wish to
handle as a continuous small signal model, you must make some provision to
handle the the phase and frequency characteristics of the sampled portion.
If the sampled portion is linear and all frequencies under consideration
are below Nyquist, such a small signal model can be used.
All PWM converters are at least in part sampled systems. In the most
common type, the switching transistor is turned on at some fixed time
interval and the delay after that to when the transistor is turn off is
what is modulated to vary the output.
For this type of converter, the input to the PWM section is only sampled
at the time the transistor is turned off. To be more exact, the input in
some very narrow span of time is used because internally a ramp is being
compared to the input signal.
Once the converter has turned off the transistor, it can't turn it back on
until this cycle is completed and the next sampling of the input is only
done at the next time the transistor is turned off.
The rate that the current in the output inductor decreases, when the
transistor is off, is near enough to a straight line that we can assume a
straight line running down to zero. If a disturbance at the input of the
modulator caused the transistor to remain on for a slightly longer time,
this line is displaced upwards (ie a higher current) and intersects zero
at a later time.
This increased current in the inductor represents the effect of the
disturbance and most of it is at a time later than the sampling which
occured at the instant the transistor was shut off. This is proof that
there is a delay but it does not prove that the "transport dealy" model
best models this. I will now undertake that subject.
If the disturbance is assumed to be a sine wave at the input of the
modulator and is further assumed to be below Nyquist, there is no
mechanism by which the frequency of this waveform can effect the amount of
delay and therefor the delay must be constant. It is also obvious that
the amplitude of the resultant output current caused by the disturbance
is independant of the frequency of the disturbance. Therefor we have a
constant amplitude and constant delay time so the "transport delaY" model
is the correct one to use.
