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CPLD Configuration

Discussion in 'Electronic Design' started by [email protected], Mar 9, 2007.

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  1. Guest

    I have a number of IO pins on a XC9572XL that will not be used in my
    design and I intend to tie them to ground.

    There are a number of documents on the Xilinx web site that refer to
    the User Programmable Ground (UPG) setting that these pins should be
    set to but thus far I have had absolutely no luck in finding what the
    syntax would be in making such a setting...

    Anyone know??
  2. Greg Neff

    Greg Neff Guest

    First and most important, subscribe to comp.arch.fpga.

    I don't use any design entry syntax to do this. If you go to the
    Xilinx Project Navigator, right-click on the 'Implement Design'
    process. Select properties, and find the checkbox that says 'Create
    Programmable GND pins on unused I/O'. This is an all or nothing deal.


    Greg Neff
    VP Engineering
    *Microsym* Computers Inc.
  3. linnix

    linnix Guest

    I use ise 6.2, so yours could be slightly different.

    In Implement Process Properties,
    enable "Create Programmable GND Pins on Unused I/O".

    The fitter report shows PGND instead of TIE.
  4. Guest

    Thanks, Greg. From what I was reading I expected to have to add all of
    the unused pins to the UCF file and then assign a UPG property to
    them. The Xilinx web site has a number of Docs that say to set this,
    but none that I was able to find explained how.
  5. Guest

    Thanks to you too, linnix. I wasn't sure if I would get an answer at
    all, much less two of them so quickly!
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