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Controlling 3v-5v level shifter nxp 74LVC4245A

Discussion in 'General Electronics Discussion' started by slvr00gt, May 10, 2013.

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  1. slvr00gt

    slvr00gt

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    May 10, 2013
    I am working on a memory card that uses 3.3v FeRam(FM28V100-TG) in place of 5v sram. I got the card to work, except that I get large amount of data corruption. After tracing the problem with the scope I narrowed it down to data writes. Whenever 5v side is driving 3v side I getting very noisy data. See pic. There is no noise when 3v drives 5v. I removed the FeRam to isolate the problem. First, I tried to tie DIR pin to high and the noise level decreased, but still noticeable Then, I tied OE# pin to low and DIR pin to high and data line is clean. Somehow, control signals cause the noise, but control signals themselves look clean on the scope.
    Any ideas?
     

    Attached Files:

  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    Are the control signals 3.3V or 5V? If they're 5V you could be seeing the result of input currents flowing from the control inputs to the 3.3 volt rail.

    As a temporary solution try placing a (say 10k) resistor in series with the control signals and see if the problem is much reduced.
     
  3. slvr00gt

    slvr00gt

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    May 10, 2013
    Thanks for suggestions!

    Originally, I had controls on 3.3V. I moved them to 5V rail and result is the same. I tried to play with resister, but resulting signal looked like sine wave instead of the normal pulse. It didn't help. Spec below doesn't specify the reference voltage for the control signals.
    http://www.google.com/url?sa=t&rct=...=EDy3RyyanFZOwb1iqSE86w&bvm=bv.46751780,d.cGE

    I am starting to run out of options. I ordered couple of 74LVC4245 parts from different supplier ( Texas Instruments). Spec for TI part specifies control reference voltage to be VCC(A), which is 5V in my case
    http://www.google.com/url?sa=t&rct=...=lH3AAPXbVNZCbOJgkrqN3Q&bvm=bv.46751780,d.cGE


    Any other ideas for me to try while I am waiting on TI parts?
     
  4. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    OK, yes, the rise and fall will be affected, but what do the 5V signals look like?

    I am suspecting that the FeRam inputs are not 5V compliant (is the chip still powered by 3V3?). This may cause the input signals to be diverted to the 3V3 rail or ground. Both of these *may* be causing problems.

    The other potential problem is that the chip may not be powered (or the ground connections made) and may be getting its power via the input protection diodes and decoupling capacitors. Logic can still operate like this (amazingly) but you can get weird results.
     
  5. slvr00gt

    slvr00gt

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    May 10, 2013
    FeRAM is 3v device. It is the reason for 74LVC4245 chip. I have voltage regulator for FeRam to produce 3v from 5v input. Entire interface between processor and FeRAm is level shifted, address, data, control and all. Address and control are unidirectional, going through different chip. l and I don't see any problems with uni-directional signals, all nicely shifted down to 3v. Data is bi-direction and has this problem.

    After changing control to 5v referenced I see the same problem with data as 3v referenced.

    See attached pdf with complete schematic
     

    Attached Files:

  6. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    OK, I think we're getting closer to the problem.

    If you go back to your original images. The first two both show a problem in the top trace. I actually think the second one is more revealing. Note how the logic levels droop?

    I've got a copy of your diagram ere, can you tell me where you read these signals, and which chip was removed, and which chip (was it U21?) that had the DIR and OE pins forced to a particular value?

    Is it possible that the ground pin of U21 is not connected? The various Vcc connections are shown, but not ground. Just checking other chips, you're showing the ground connections explicitly, so I would expect to see them for U21.

    U26 and U21 both have ground connections not shown
     
  7. slvr00gt

    slvr00gt

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    May 10, 2013
    First image shows the DATA7(5V) and 1_DATA7(3V) read out from J1 header. 1_DATA7 is noisy one.

    Second image shows 1_DATA7(3v) on the top with the droop. It is read out from the same header. Second image was taken after I tied high DIR signal of U26 while keeping OE# connected in the circuit. U21 is the second instance of 74LVC4245 with both DIR and OE# tied to make it unidirectional. No problems with U21. 5v and 3v sides of the U21 circuit are nice and clean.

    Good guess about the GND on U21 and U26. It is connected through. See another footprint image of U21 and U25.

    One of the experiments I did was removal of FeRam chip U24 to isolate the problem to transceiver. Another FeRam, u25 was never populated.

    What does the droop on the second image tells you?

    I appreciate you helping me out with this!
     

    Attached Files:

  8. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    It is strongly suggestive of a very high impedance connection of the chip creating this signal to the power supply. It is as if the power is coming from the bypass capacitor or similar.

    The first image looks like the same thing, except the voltage source stays very low and signal seems to float all over the place.

    Perhaps you can monitor the voltage to the various chips directly from their supply pins. (could one have a bad connection to the supply or ground?)
     
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