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Control unit design for solving linear equation computing unit.

Discussion in 'Electronics Homework Help' started by prat, May 3, 2018.

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  1. prat


    May 3, 2018
    The agenda of this task is quite long and I'm trying to be as elaborate as possible. This is the exact question given to me and I do have an idea of how to go about it, but I have doubts regarding very intricate details such as bus tapping and bus width issues.

    The question asks, design a digital system that computes the value of the following equation:
    f(x) = (1 + x + y + z*t) / 2.

    The system is divided into the control unit and the processing unit which computes the result. The control unit and the processing unit follow a system of handshaking procedures.

    My question as of now is, in the given situation is with the processing unit.
    I have used the following components and i have to simulate the same on xilinx and VHDL.
    Screenshot from 2018-05-03 22-59-49.png
    The image above is the flowchart for the processing unit to compute the expression. The image below is the schematic for the same.

    Screenshot from 2018-05-03 23-12-23.png

    The flow:
    1. REG T load enables and the T is loaded to the register.
    2. REG Z load enables and the Z is loaded to the register.
    3. Z and T is multiplied using shift and add method and is added to the REG R.

    4.REG Y is load enabled and the value is loaded and Y is added to REG R. Which stores the value of Y + (Z * T).
    5.REG X is load enabled and the value is loaded and X is added to REG R. Which stores the values of X + Y + (Z * T).
    6.The carry in on the added is set to high to add '1' to the result in REG R. Which stores the value of 1 + X + Y + (Z * T).
    7.The bus is right shifted by wire method to divide by 2. Thus the result 1 + X + Y + (Z * T) / 2.

    My Question:
    1. Is anything unclear to you as a reader?
    2. How to do i get the bus widths rite? in Xilinx while creating the schematics?
    3. What could be wrong? I need some validation for my flowchart and schematic.
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