Conformal Tool in FPGA Full CHip design

[nohj_yar]

HI All! Im a beginner in this forum and currently studying as a MS student. Im studying Cadence COnformal tool to check the equivalence of RTL to gate-level netlist. Now I've done the latter. My question is that is there any possible way to check the formal equivalence of a gate-level netlist or (RTL netlist) versus FULL CHip FPGA netlist?