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Conformal Tool in FPGA Full CHip design

Discussion in 'Microcontrollers, Programming and IoT' started by nohj_yar, Jan 16, 2015.

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  1. nohj_yar

    nohj_yar

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    Jan 16, 2015
    HI All! Im a beginner in this forum and currently studying as a MS student. Im studying Cadence COnformal tool to check the equivalence of RTL to gate-level netlist. Now I've done the latter. My question is that is there any possible way to check the formal equivalence of a gate-level netlist or (RTL netlist) versus FULL CHip FPGA netlist?
     
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