# Comparing two slow reference clock frequencies

Discussion in 'Electronic Design' started by arant, Aug 14, 2006.

1. ### arantGuest

Hi Everyone,

Does anyone have any idea of how to compare two reference clock
frequencies using digital logic only .

The problem is something like this .There are two slow ref clocks Khz
range CLKA (RC oscillator clock) CLKB (crystal oscillator clock) and a
fast sys_clk (pll clock) Mhz range

If freq CLKA > freq CLKB then
op1 = 1
elsif freq CLKA < freq CLKB
op2 = 1
else
op3 = 1
end if

One solution that I can think of is running two parallel counters on
the sys_clk for one period of the CLKA (count a) and CLKB 9ount b) and
comparing the count values

if count a = count b then
op3 = 1
elsif count a > count b then
op2 = 1 -- freq CLKB > freq CLKA
else -- freq CLKB < freq CLKA
op1 = 1
end if

Is there a better way of doing this instead of using teo parallely
running counters
An optimum solution in terms of area will be highly appreciated

Eagerly awaiting some solutions

2. ### LuhanGuest

How about just using the phase detector in a PLL?

Luhan

3. ### Ancient_HackerGuest

How quickly does this comparator need to respond? One cycle? One
second?

The simplest way I can think of is to get an up-down counter chip. Set
it up so it counts up clock1 for a while, then counts down clock2 for
the same while. If it underflows, then clock2 > clock1, otherwise
clock1 > clock2.

4. ### Ulrich BangertGuest

Most phase detectors are only phase but not frequency responsive. Look at
the functional block diagram of a AD9901 and cover it in whatever logic
family that you may have available.

Regards
Ulrich Bangert

5. ### arantGuest

Thanks guys for your suggetsions but the problem is the solution has to
be manged in the digital (sic) domain only i.e no phase comparators et
al
The requirement is for an SoC clock manager that generates an
interrupt/event to the CPU based on the clock comparison operation.

6. ### arantGuest

How quickly does this comparator need to respond? One cycle? One
Well there is no stringent response time requirement for the comparator
but the minimum possible is the best
I think using two parallel counters instead of one would reduce the
response time latency but at the cost of area ...

7. ### vasileGuest

I don't know what microcontroller/DSP/microprocessor system are you
using, but usually this is done with a compare/capture feature. PIC
series has such a module
which is able to compare an unknown period with a timer period and
switch a flag as required.

greetings,
Vasile

8. ### PeteSGuest

Phase detection can be done purely in the digital domain - see this
datasheet for an example of a standalone device:

Cheers

PeteS

9. ### Ken SmithGuest

Can't you use a digital phase comparitor? Its only a few flip-flops.

10. ### arantGuest

Can't you use a digital phase comparitor? Its only a few flip-flops.

I would if I knew what it was as far as I know there is a XOR gate or a
JK f/f that act as phase comparators in the digital domain

11. ### Ken SmithGuest

Simplest type:

If the signal is a square wave, you can just apply the signal to the "D"
input of a flip-flop and clock it with the reference. This way you latch
the state of the input at the edge of the reference and thus whether or
not it has gone high before the reference. This type only works for
signals of nearly equal frequencies. If one is a multiple of the other,
it will tend to lock you to the harmonic.

The double flip-flop type is call a "three state phase detector".

This is the basic idea of that type:

ASCII art:
-------! \
! !AND>----BOTH
! ---! /
-------- ! !
True--!D Q!----+----------! \
Signal -----!> ! ! !AND>---- Early
! R Q!O--- ! ---! /
-------- ! ! !
! ! ! !
BOTH ----- ! ------! \
-------- ! ! !AND>---Late
True--!D Q!--------+- ! ------! /
Ref -----!> ! !
! R Q!O----------
--------
!
BOTH

Depending on the phase, you get a pulse on "early" or "late" for each
cycle.