# common emitter configuration- voltage divider biasing.

Discussion in 'Electronic Basics' started by Jenny, Jul 26, 2004.

1. ### Ian BellGuest

Very true, but this was not the OP I thought it was worth a quick mention.
The bottom line really is that a CE configuration is an excellent vehicle
for a tutorial because its limitations soon become clear, which leads
naturally to other transistor configurations.

I am very pleased people are prepared to question basic assumptions in oder
to better there understanding. What really irks me is that you still see
really poor CE designs in the popular hobby electronics magazines.

Ian

2. ### JoeGuest

Hi Jon,

Yes, I read it, and some of it is below, in quotes:

"What I didn't like about the web site is that the C they used simply
bypassed
their emitter R, so that the transistor's emitter then went straight to
ground.

It's not a typical arrangement for audio. I'm not even sure what it would
be a
good approach for."

I think I understand your statements. I am just wondering, the equation they
use to get the value of the emitter cap is:

Ce=1/(2*pi*F*Re)

where F is the minimum frequency you want to pass, and Re is the emitter
resistor. Also, they say that this would be the minimum value cap you
would want to use, so I usually use the next higher standard value.

Is this equation incorrect? If so, do you know what it should be?

I am a hobbyist, not an engineer, but I like to find out the best ways to
design different things, and I can imagine that with some situations, maybe
it is a little 'black art', or engineering intuition that goes into a
design, but I do not possess any of that so I have to rely on equations.

Best Regards,
Joe

3. ### Jonathan KirwanGuest

The whole idea on that page is wrong, I think. The very topology is wrong, to
my mind. Since I don't understand what their application might be, I cannot
possibly correct their equation. I'd need to know what in the heck they were
thinking, before I could even consider it.

I can, however, tell you how to calculate it for the topologies I had in mind
and pointed out in another post... because I think I understand them to a
degree.
I'm just a hobbyist, too. Zero professional design experience. Perhaps like
you, math and physics are my joys.

Jon

4. ### JoeGuest

Hi Jon,

This is becoming an interesting discussion. From what I can understand, the
emitter cap is there to shunt (if that's the right word) certain frequencies
to ground so they don't get amplified. But when you figure out the cap, you
have to use the lowest frequency you wish to eliminate (shunt?), and then
all frequencies higher than that also get eliminated. So is it sort of a
low pass filter? One other thing I noticed about using their equations is
that the emitter resistor is almost always 10% of the collector resistor. I
started using their method because I didn't know how to calculate the bias
voltage divider for some transistors I couldn't find the curves for. Then I
started to incorporate all their equations into my spreadsheet so that now I
can build one from input to output. They made it easy, all you need to enter
is the hfe, Vcc, desired collector current and frequencies to pass.

..
Joe

5. ### Kevin AylwardGuest

No. Quite the oposite.
No, the lowest frequency you want to *include*.
The circuit forms a HP filter.

The object is to get the input signal directly across the base-emitter
junction. This maximises the signal to the transistor, hence the current
that will flow through it. The emitter impedance attenuates the signal
to the base emitter such that Vbe = Vsig.re/(re+Ze). Ze wants to be as
low as possible.
As I have noted, this can all be done automatically in SuperSpice,
http://www.anasoft.co.uk/DeviceDesigner.html:-)

Kevin Aylward

http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

6. ### Ian BellGuest

Joe wrote:

snip
As the capacitor is across the emitter resistor which provides negative
feedback, the frequencies that the emitter capacitor shunts are amplified
*more* not less.

Ian

7. ### Jonathan KirwanGuest

Like I said before, I don't really understand the use of the topology shown at
that site. Given what they drew there, of course, as the frequency increases,
the shunting gets more pronounced.

But the problem as I see it in that example is that if the capacitor is sized to
effectively bypass the emitter R at some low frequency and for those frequencies
above that point (until other factors dominate and change what I'm about to
say), then the emitter is essentially grounded above that frequency point. So,
let's say you size it to bypass the emitter R at 100Hz and above, then for those
frequencies the Z of the capacitor will be diminishingly tiny and the emitter
will be, in effect, at ground.

This isn't a good thing, usually. What it means is that the gain is then based
on R(C)/(r(e)+Z(c-bypass)) and, since r(e) is highly dependent on I(C), the gain
will be varying all over the place. Similarly, if the Z of the capacitor hasn't
yet diminished to the point where it is very much smaller than r(e) itself, then
the frequency will also be varying the gain all over the place, too.

It's not good.
You would use the lower frequency that you want to shunt, yes. But that is the
reverse way to look at it. You are actually setting the lower end of the
__desirable__ frequency band. Frequencies less than this will get smaller gains
and will therefore diminish in their relative presence in the output because
they are NOT bypassed by the C.

Here's a better topology (not the only one, though):

V+ V+
| |
| |
| |
\ \
/ Rb1 / Rc
\ \
| |
| +--------> OUT
| |
| |
| b|/c Q1
+-------| NPN
| |\e
IN >-----+ v
| |
| +-------,
| | |
| | \
| | / Rac
| \ \
\ / Re |
/ Rb2 \ |
\ | |
| | --- Cac
| | ---
| | |
| | |
--- --- ---
gnd gnd gnd

Without getting into more complex models, gain is:

Rc / ( r(e) + ( Re || (Rac + Z(Cac)) ) )

Here, you can see that Cac acts similarly, but that when its Z is tiny, then the
resulting gain is set by Rc/(r(e)+(Re||Rac)). (|| means the parallel equivalent
resistance.)

In other words, you design the DC operating point by ignoring Rac and Cac, at
first. Once the DC operating point is established in that way, then you design
Rac and Cac so that when the frequency rises above some given point, Cac will be
an effective bypass, tying Rac to ground. But NOT the emitter itself!

That way, you can design this to have a predictable gain that doesn't vary much
over I(C) or over frequency, once that low frequency is reached (and beyond)
because you can arrange things so that (Re||Rac) is still large compared with
r(e) "little r-e" and also that Rac is large compared to the Z of Cac at and
above some design frequency. Since (Re||Rac) also isn't dependent on the
frequency at all because the Z of Cac is also diminishingly tiny by comparison,
the gain can be made relatively stable over a wide range of frequencies.
No, the other way around. Since frequencies lower than this set a high Z, the
gain of the amplifier at those still lower frequencies declines until the Z is
very much greater than the emitter resistor and that emitter resistor then sets
the low gain limit. Since higher frequencies have a higher gain (and in that
web site's design, a continually rising gain that doesn't make sense, usually),
they appear more dramatically in the output.
Well, in general, you usually want some gain! If the emitter resistor were
larger, you'd be attenuating the signals instead of increasing them. Sometimes,
that's what you want. But not here, I think.
I went through some of the calculation steps in detail, earlier. Did you read
them? Did they make any sense? Also, most small transistors (BJTs) can work
just fine on a quiescent I(C) of anywhere from 0.4mA to 20mA, and probably even
wider than that. If you want to just play and aren't designing anything in
particular, I'd pick a quiescent I(C) of 1mA and build up a circuit on that
basis.

Like others have pointed out, a real design will need to account for what is
driving the circuit and what the circuit is supposed to drive, itself. For
example, if you are driving your 'test' amplifier circuit from an oscillator or
even a square wave generator, then how are you going to hook that up? Do you
imagine just tying one end to ground and the other end to the supposed input at
the BJT base? Through a resistor of some kind? Through a capacitor of some
value? How? And some inputs, like say a microphone or some other kind of
transducer, may have very particular requirements in order to operate well.

Usually, you have some kind of circuit designed to accommodate your transducer
and allow it to operate well. So that circuit is designed to meet the need of
the transducer and reflect the signal accurately into the next stage, which
often IS designed for some gain. But the first stage/circuit is more designed
for the transducer. Then you might have several stages of voltage amplification
after that. Finally, followed by yet another circuit designed for the type of
output transducer -- for example, such as a speaker. That last stage will again
be tailored for the output transducer and not for voltage gain, itself.

In the above case example I gave, where the amplifier is designed for voltage
gain at some AC frequency and above, it might look more like:

V+ V+
| |
| |
| |
\ \
/ Rb1 / Rc
\ \
| |
| +--------> OUT
| | (perhaps to another capacitor input)
| |
| b|/c Q1
+-------| NPN
|| | |\e
IN >----||---+ v
|| | |
| +-------,
Cin | | |
| | \
| | / Rac
| \ \
\ / Re |
/ Rb2 \ |
\ | |
| | --- Cac
| | ---
| | |
| | |
--- --- ---
gnd gnd gnd

Cin would be sized, like Cac, to pass frequencies above some point very well.
Using a capacitor there allows the DC biasing network to do it's job and
correctly bias Q1 and to maintain that bias as higher frequency signals are
passed on by Cin. Any DC setpoint from the input side of Cin won't pull down or
pull up the DC biasing -- it will simply charge Cin and leave it charged.
I've done similar things with LTSpice.

Jon

8. ### John PopelishGuest

(snip)

That depends on what you need. Its big advantage is maximum (if
variable) gain.

9. ### JoeGuest

Hi Jon,

Ok, so, judging from the other responses, I have been looking at things sort
of bass ackwards

I was thinking that the emitter cap would in most cases be shunting out
unwanted frequency. Say for audio, you want from 20hz to 20Khz but get rid
of anything above 20Khz, so you calculate your Ce for 20Khz. Now I can
understand a little better that the Ce is actually feeding back those
frequencies to get more gain. OK, again I was looking at it wrong. In this
case, you would choose the emitter resistor to pass all frequencies above
20hz to get your audio amplification.
OK, got it.
So do I read the above correctly? Cac is in series with Re? I am not too

OK, understood, the problem I was having was with choosing the DC operating
point. I use mostly small signal transistors , but usually just as a switch.
I wanted a general set of equations that I could use for any common emitter
application.
Probly the best thing for me to do is LTspice some of these circuits and
look at the output waveforms, and then possibly breadboard them and check
them on the scope. I have not built many common emitter amps so maybe I need
to do that.
My point was just why 10%? If it were 20 or 30 or 50%, there would still be
some gain. I am probly trying to generalize too much to make designs easier.
Yes, they made sense to me, but, as you can see, I was not thinking quite
right. :-(

Also, most small transistors (BJTs) can work
That is probly a good idea, as I mentioned above, there's no substitute for
experience.
They show how to compute the value of the input cap, and output cap, but
don't really explain if a resistor is needed.

How? And some inputs, like say a microphone or some other kind of
I think I am getting lost now. I cannot read the above schematic, but I have
never seen a DC setpoint on the input side of an input cap. The cap would
block it wouldn't it? Then there would be no biasing on the transistor, it
may just act like a switch depending on what frequency is input to it.
I think I will be using LTSPICE more often (it is quicker than
breadboarding, but I figured it wouldn't always reflect the real world) and
trying different configurations using the equations and then just picking a
bias current as you stated earlier and see what the differences are.

Thanks for your patience explaining this to me. Thanks to everyone else who
replied. I am getting clearer on this now.

Joe

10. ### Jonathan KirwanGuest

Joe,

Are you using a FIXED SPACED font when you read the ASCII schematics??? This is
seriously a BAD THING if you are using a proportional spaced font. Try one of
the Courier, Pica, or Prestige Elite fonts, for example.

Jon

11. ### Jonathan KirwanGuest

....at some frequency and above. Of course, I'm still struggling to understand
an application where this is "good." -- both setting up a DC operating point
like this AND arranging for an 'uncontrolled' AC bypass like this? Know of a
serious one? I'm curious.

Jon

12. ### Rich GriseGuest

I slapped together a little mic preamp by the seat of my pants doing
exactly that. I didn't care too much about gain, just so it was "enough."
(maybe 3-5, actually.) I used a 10K pot for output, 1K emitter R, about
220K and 820K for base bias, and I think a 10 uF right across the 1K Re.

It was "good enough" for voice, anyway.

Cheers!
Rich

13. ### Jonathan KirwanGuest

Well, why wouldn't you add a resistor in that leg so that you got a nice, flat
gain over a range of frequencies, rather than a highly distorting gain depending
on the signal level's voltage AND also it's frequency? I mean... a resistor is
all it takes, for gosh's sake!

And we aren't talking about 'good enough' for some uses. That web site is a
little more than about hacking something together that might vaguely work... in
some kind-of way. They are trying to explain things and provide design
explanations. So again, why didn't they include the resistor?

Remember, I'm asking about good design. In what application is that circuit
"good," as a matter of design?

That site still just doesn't make sense to me.

Jon

14. ### Robert C MonsenGuest

Just to throw in my 2 cents, as I understand it, the emitter resistor
bypass cap is there to increase the gain as the frequency increases.
The gain of the amp is equal to the collector resistor divided by the
effective emitter resistance. If you put in a cap parallel to the
emitter resistance, what happens is that at higher frequencies, that
effective emitter resistance decreases (the cap 'shunts' or shorts the
higher frequency currents to ground.) Thus, doing this increases the
gain of the simple common emitter amp.

Somebody asked why you might want to do this. I think the answer is
that these days, if controlled gain is required, its generally
accomplished by using negative feedback. Negative feedback is more
effective if the open loop gain is higher, so getting the highest gain
you can is a good thing, even if you aren't able to control it very
effectively.

All of this is described quite well in "The Art of Electronics", 2nd
edition, chapter 2. If you really want to understand how all this
stuff works, or at least get a basic understanding of how to work the
formulas and bias an amp, go check out that book from the library and
read chapters 1 and 2. The feedback discussions are in chapter 4, I
think, and are also well worth the work.

Regards,
Bob Monsen

15. ### Kevin AylwardGuest

Its done *all* the time when you use overall negative feedback. In this
case, you don't care what the gain is, only that it is as large as
possible. Indeed, all op amps are pretty much designed to have
'uncontrolled' dc and low frequency gain. Its only the compensation
capacitor that reign in the gain.

Its also done when you have very low signals and desire the utmost in
low noise. Any resistance in the emitter circuit will add noise.

Kevin Aylward

http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

16. ### Ian BellGuest

I think you should consider this topology simply as an example to enable
people to understand the basic trade-offs in transistor circuit design. it
is *not* a topology that would normally be used in a proper design.
However, once you understand the limitations of a simple CE circuit you can
start to grasp the more common multi-transistor configurations.

Ian

None.

Ian

18. ### Rich GriseGuest

Well, like I said, it was good enough for the app. I just didn't bother,
I guess. I hope I'm forgiven.
Others have mentioned a gain stage in an amp with overall negative
feedback, which makes sense to me, but I can't take any credit for
noticing it.

Cheers!
Rich

19. ### Jonathan KirwanGuest

Thanks, Kevin. In other words, when you wrap the stage(s) with a feedback loop.
Yes?
Ah. Of the (4kTBR)^.5 variety.

I can think of cases, rather easily, for your first paragraph. So I'm with you,
there. But in the second case, can you suggest a specific application that I
can consider more closely (one where the overall negative feedback is NOT used,
but where noise needs to be minimized in this way?)

Jon

20. ### JoeGuest

Hi Jon,

My default font says it is 'courier new' whatever that means.

Joe