Connect with us

CMOS VLSI Q&A

Discussion in 'General Electronics' started by Jae Purvis, May 14, 2004.

  1. Jae Purvis

    Jae Purvis Guest

    Please posts your questions and answers from anything from MOS device
    theory, processing, and design. I'd like to see what comes of it. I'm
    not exactly an expert in VLSI but I'm always looking to know more.

    Someone asked me a simple question the other day concerning the
    limitation of increasing the power supply to reduce delays. My
    explanation is that once you increase the supply voltage at the drain
    terminal, the depletion region should extend to the source. This
    means there should be no carriers at the surface for conduction in
    the channel area. Thus carriers are swept across the channel to the
    source independently of gate voltage(i.e. when vgs=0) at the
    saturation velocity. Someone verify if this is the limitation. This
    condition should be avoided however......

    at submicron level, such small geometries invite punchthrough and hot
    carrier problems. Can someone explain how to avoid these problems say
    for 5V supply? I know that by grading the doping concentration away
    from the oxide is one way of getting rid of hot carrier problems.
    Another possible solution could be reduce the internal circuit
    voltages so that these problmes do not arise. Any input would be
    appreciated.
     
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-