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cmos-logic -- low dynamic power dissipation

Discussion in 'Electronic Design' started by Winfield Hill, Sep 1, 2005.

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  1. TI's new 74aup line of cmos logic gates features dramatically-lower
    dynamic power consumption. (As you should know, cmos logic has zero
    DC power usage, so dynamic "ac" power consumption is what matters.)

    For example, TI's 74aup1G14 cmos IC is a single-gate Schmitt-trigger,
    http://focus.ti.com/docs/prod/folders/print/sn74aup1g14.html and its
    power-dissipation capacitance (Pd = f C V^2) is an amazingly-low 4pF
    (for Vcc = 0.8 to 3.3V). Compare to 9pF for TI's older 'ahc1G14
    part, 10pF for ON Semi's 74hc1G14 part, 12pF for the Philips part,
    and 21pF for TI's 74lvc1G14 and ST's 74v1G14 parts, just to take a
    few examples (ditto for their 74aup1G125 buffer, etc., only 4pF).

    When used at 0.8V, TI's 74aup parts are real power-consumption misers.
    Make a low-power Schmitt-trigger relaxation oscillator, and all kinds
    of other cool stuff. Hmm... I wonder what the competition is doing.
     
  2. What i really like on this ultra low voltage stuff is
    how to interface to normal logic. This is where the
    part count goes up.

    Rene
     
  3. Chris Jones

    Chris Jones Guest

    Doesn't the Schmitt-trigger gate draw extra current because its input is
    operating near the threshold? (ok, the threshold keeps moving, but I
    thought that each time you approach it, the supply draws more current.) I
    wonder if there is a way around this. If you could run the supply at less
    than the sum of the N-ch and P-ch threshold voltages, that would be a
    start, but then I think Schmitt triggers don't work under that condition.

    Chris
     
  4. Chris Jones wrote...
    Actually, you raise a point, which is that the dynamic power-dissipation
    capacitance is measured with fast-risetime full-logic-swing test signals
    applied to the gate. Obviously a Schmitt-trigger gate (or any gate) will
    draw much more current when operating with a low-voltage slow-risetime
    input. You may be able to infer an improved performance for these parts
    under such a conditions, but you won't be able to come up with an actual
    number from the datasheet specs.
     
  5. In general, bipolar transistors usually beat out CMOS for ultra low
    power oscillators.


    --
    Many thanks,

    Don Lancaster
    Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552
    voice: (928)428-4073 email:

    Please visit my GURU's LAIR web site at http://www.tinaja.com
     
  6. Guest

    I measure 700uA @ Vdd = +4V for this fellow (below), and about half
    that at Vdd = +3V.


    ' R1 68k
    ' ___ D1
    ' .-------|___|-----|<----.
    ' | |
    ' | |
    ' | R2 2meg |
    ' | ___ |
    ' o--------|___|----------o
    ' | |
    ' | __ |
    ' o---------| \ |
    ' | | )o--------+--> 600uS x 66Hz
    ' | Vdd ---|__/
    ' |
    ' --- 74hc132
    ' --- C1
    ' | 22nF Vdd = +4V
    ' | Idd = 700uA
    ' GND

    (created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

    Regards,
    James Arthur
     
  7. wrote...
    Those numbers are in line with some of the datasheet graphs for
    74hc132 current consumption for linear inputs, such as those in
    the Philips datasheet. We can speculate how TI's new 74aup parts
    might fare by comparison. Their 4pF power-dissipation capacitance
    is 3 to 8 times lower than the power-dissipation capacitance specs
    for various manufacturer's 74hc132 parts, which is one comparison
    factor, and they can be operated at much lower voltages, which is
    another.
     
  8. Jim Thompson

    Jim Thompson Guest

    Tapered turn-on/off output stages. First developed for ground bounce
    reasons.

    ...Jim Thompson
     
  9. Jim Thompson wrote...
    Please give us a detailed tutorial. Thanks in advance.
     
  10. Jim Thompson

    Jim Thompson Guest

    Pretty trivial, once you see it...

    Imagine an RC delay line with an MOS gate at each tap. Size the
    delays and device sizes appropriately and you can create just about
    any shape of rise and fall time, with appropriate reduction in current
    spike... my favorite, of course, is TANH ;-)

    ...Jim Thompson
     
  11. keith

    keith Guest

    Sure, but a schmitt trigger's feedback will insure that it's in the linear
    range for a short period. CMOS conducts massively in the
    linear/crossover/shoot-through region. Once the output snaps it should
    draw very little current. A schmitt trigger should make a slow input
    far less of a problem (the gain thing).
     
  12. keith wrote...
    Not quite. After the output snaps the output stage will draw very
    little current, but the input stage, which was the current-drawing
    offender to begin with, still draws substantial current, and it will
    continue to do so until the *input voltage* moves well away from the
    trigger voltage. The Philips datasheet shows this effect clearly,
    especially if the part is operated at 5V. Lower-voltage parts do
    better, but the 74LV132 still shows this effect when operated at 3V.

    http://www.semiconductors.philips.com/acrobat/datasheets/74HC_HCT132_CNV_2.pdf
    http://www.semiconductors.philips.com/acrobat/datasheets/74LV132_3.pdf

    It would be interesting to see such a plot for TI's new 74aup1G14.
     
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