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CMOS inverter dynamic behavior!

Discussion in 'Misc Electronics' started by Francesco, Jun 24, 2006.

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  1. Francesco

    Francesco Guest

    I'm studyng CMOS inverter dynamic behavior, and in my book I read at
    first that the two transistor NMOS and PMOS ohw compose the inverter are
    forbidden or in saturation for all the first half of the logical
    excursion (until the 50%)

    I think that ,for example if at the output I have logic level H (VDD)
    and I turn on the NMOS, it is in saturation until VDS>=VDD-VT (VT is the
    threshold voltage), then it go on linear mode.

    Obviously the same situation for the PMOS in the L-->H excursion.

    What I don't understand?

    Sorry for my english!

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