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CMOS Differential Amp question

Discussion in 'Electronic Design' started by [email protected], Mar 12, 2007.

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  1. Guest

    Hi!

    What is the maximum and minimum input voltage of a CMOS differential
    amplifier with active loads with respect to the power supply rails?

    Thanks.
    Amy
     
  2. Guest

    It varies from device to device. If you have a particular CMOS
    differential amplifier in mind, you can go to the manufacturers web
    site, and down-load the data sheet for that device, where this
    information is available.

    Look for the input common mode range - which is the range of input
    voltages for which the amplifier outputs will mean something useful.

    The inputs can usually survive a wider range of input voltages, but
    the output voltages can sometimes behave rather oddly for extreme
    input voltages.
     
  3. Eeyore

    Eeyore Guest

    I suggest you read the data sheet. They're all different. I don't see why the
    load makes a differnce btw.

    What's your actual problem.

    Graham
     
  4. Eeyore

    Eeyore Guest

    Including inversion !

    Graham
     
  5. Just a note: Mr Murphy never fails. Active load will display negative
    resistance at some part of its response curve at some frequency and
    beying in feedback sensing cirquit gives you the s**ts.
    Stanislaw.
     
  6. Rich Grise

    Rich Grise Guest

    Mid-terms. ;-)

    Cheers!
    Rich
     
  7. Guest

    Hi! Thanks for your replies. What I meant was active load of
    differential amplifiers in integrated circuit design, not discrete
    amplifiers.
    An example of a differential amplifier with active loads can be found
    at:

    http://www.deas.harvard.edu/courses/es154/pdf/lecture12.pdf
    Slide 22

    Thanks.
     
  8. Guest

    AKA phase reversal. A risk often encountered when using an op amp for
    a comparator.
     
  9. Guest

    AKA phase reversal. A risk often encountered when using an op amp for
    a comparator.
     
  10. Guest

    Hi! Thanks for all your replies. What I meant was differential
    amplifiers in integrated circuit design, not decrete amplifiers.
    An example of an differential amplifier with active load can be found
    at this website:

    http://www.deas.harvard.edu/courses/es154/pdf/lecture12.pdf
    Slide No. 22

    Can someone with IC design experience please help me?

    Thanks.
     
  11. Guest

    AKA phase reversal. A risk often encountered when using an op amp for
    a comparator.
     
  12. Jim Thompson

    Jim Thompson Guest

    What is the question?

    ...Jim Thompson
     
  13. Rich Grise

    Rich Grise Guest

    AKA phase reversal. A risk often encountered when using an op amp for
    a comparator.[/QUOTE]

    Inversion is NOT "phase reversal" - the output is precisely in phase,
    (within the freq. limits of the amp), simply inverted in polarity.
    Phase reversal requires a 180 degree PHASE SHIFT at the frequency
    in question. Inversion doesn't do that.

    Now, admittedly, the graph of -sin(t) _LOOKS EXACTLY LIKE_ sin(t + 180),
    but they _ARE_ different. The second version (sin(t + 180)) requires
    some kind of memory of the previous state - -sin(t) doesn't.

    Cheers!
    Rich
     
  14. Guest

    Hi Jim,

    I want to know the maximum and minimum input voltages that can be
    applied to the differential amplifier with respect to the power
    supply.

    Thanks.

    Amy
     
  15. Jim Thompson

    Jim Thompson Guest

    Presuming P-type substrate, the inputs can't go below ground without
    forward biasing the NMOS body diodes.

    There are two possible scenarios in the positive direction...

    With no ESD structures in place: You can go as positive as allowed
    before the gate oxide punctures (breaks down).

    With ESD structures in place: If you go above the positive rail these
    diodes will conduct.

    If the question really is what is the linear operating region it
    depends on many individual device parameters and the load at Vo.

    If there's no load at Vo, it's characteristics will be
    comparator-like.

    Hope that helps.


    ...Jim Thompson
     
  16. Rich Grise

    Rich Grise Guest

    Please don't top-post: It interrupts the natural flow of the thread.

    In answer to your question, have you actually read the data sheet? It
    should be called out clearly.

    Good Luck!
    Rich
     
  17. rush3k

    rush3k Guest

    for max input, you start from top rail (vcc/vdd) and subtract all the
    threshold and overdrive voltages in the path from vcc/vdd to vin ...
    and same applies to vee/vss/ground ... look at gray and meyer's
    analysis and design of analog ics
     
  18. Guest

    for max input, you start from top rail (vcc/vdd) and subtract all the
    Hi rush3k,

    Tell me if I am right.

    Referring to my diagram at http://www.deas.harvard.edu/courses/es154/pdf/lecture12.pdf
    Slide 22, from the top rail minus one threshold voltage of the PMOS is
    the maximum input voltage.
    one threshold voltage of the input transistor. That is the minimum
    input voltage.

    Thanks.
     
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