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cmos 74hc debounce pull up resistors

Discussion in 'Electronic Design' started by usao, Feb 26, 2008.

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  1. usao

    usao Guest

    I am looking to use a SPDT switch (center GND) with the NO and NC
    contacts wired to the inputs of a 74HC00 CMOS NAND gates.
    Is it necessary to tie both (NO and NC) inputs to power through a pull-
    up resistor? I have seen this done on TTL circuits, but I thought that
    the inputs on the CMOS had such high resistance that it would not be
    necessary. Yet, I also read in many places that the inputs of a 74HC
    cannot be left floating.
    So im going to assume they need a pull-up resistor. Is there any way
    to figure what the proper resistor value should be to ensure the input
    is not in the invalid-zone between a logic 0 and logic 1 on the input?
    Is this done simply by computing the desired voltage drop accross the
    resistor? If so, the voltage drop would be very small and the resistor
    would have a very low value, but this would lead to high current draw
    on the input pin which is grounded through the switch... What's a good
    value for a pull-up on a 74hc part?
     
  2. Eeyore

    Eeyore Guest

    It's certainly good practice if nothing else.

    With CMOS btw, it doesn't matter if you tie up or down. Whatever suits you.

    Graham
     
  3. Eeyore

    Eeyore Guest

    You're missing the point.

    Yes, because if they somehow accumulate some electric charge, the resulting
    potential on the input capacitance can cause punch-though of the insulating
    oxide layer. This is not a good thing.

    Graham
     
  4. usao

    usao Guest

    Ok, I see that the issue is static build-up. I understand that
    floating the input could endanger the chip.
    Given that I need to tie to either ground or power, how does one
    determine the value of the resistor?
    If all I need to do is avoid static charge, then a large resistor
    could be used, thus keeping my current draw through the switch to a
    minimum (it's a battery powered circuit).
    Is there a specific resistance or some range of resistance which is
    reasonable for a pull-up or pull-down resistor?
    Do I just pick any old resistor value out of a hat?
    Im searching for the criteria to determine what the value should be.
    Ron
     
  5. I assume you're using two cross-coupled NAND gates to debounce the
    SPDT switch.
    Yes, you need two pull-up resistors-- one for each input-- to make the
    input high when the switch contact is open.
    Well... if you look at the leakage current specs on the gate input
    you'll get an upper bound on the resistor value. Eg.

    http://focus.ti.com/lit/ds/symlink/sn74hc00.pdf

    Ii = +/- 1000nA (max over temperature), so for 4.5V supply we should
    have no more than 1.35V drop accross the resistor, so Rmax =
    1.35V/1E-6 = 1.35M ohms, so say 1M. Higher if you like to live
    dangerously (typically, at room temperature, with no PCB leakage,
    10,000 times higher will work, so even 10M is pretty safe in many
    situations).

    But if you don't care much about power consumption, a value like 4K7
    or 10K will result in a circuit that may be less sensitive to
    electrical noise, and may work more reliably with whatever switch you
    have.
    Best regards,
    Spehro Pefhany
     
  6. John Larkin

    John Larkin Guest

    No. The chips have esd diodes that will stop the voltage from getting
    much past the rails. The real issue is that the input logic levels are
    undefined if the input pins float. Picoamps of leakage might
    eventually pull a pin high or low at random. And if the input hangs
    midwat between Vcc and ground, the input transistors could get hot or
    the gate might oscillate.

    1K, 10K, 100K, anything like that is fine.



    Or do this:


    SPDT switch

    +5-----------o
    \
    \
    o----Rs-------------cmos gate input


    gnd----------o


    Which is esd safe, uses zero power, and is debounced.

    Rs, roughly 100 ohms, is optional to source-terminate the trace to the
    gate if it's long and ns ringing might matter


    John
     
  7. usao

    usao Guest

    Help me out a bit on this circuit...
    The SPDT switches come in 2 flavors. Shorting and non-shorting...
    If I use a shorted switch, then I will cross the rails for a few
    microseconds.
    If I use a non-shorted (ie break-before-make) then the input is
    floating...
    This is what I was trying to avoid, ie a floating input... Regardless
    of it it's because of unpredictable output or because of static
    doesn't seem to matter much, it's somthing I just don't want to do.
    Also, if Rs is a low value, then will that cause any additional gate
    current or is the gate current basically 0 anyhow regardless of the
    size of Rs?
    Ron
     
  8. Fred Bloggs

    Fred Bloggs Guest

    Do this and you have crackling sharp debounced switching, zero current
    through the resistors, and a calculation-free process capable of
    handling a SPDT or (ON)-OFF-(ON)...
    View in a fixed-width font such as Courier.
     
  9. usao

    usao Guest

    Looks interesting. I can see how the resistor would only be accross
    both rails for a short time spike, otherwise it would be neutral, with
    a logic 0 (or logic 1) on both sides of the resistor while the switch
    is stable.
    This avoids the static pull-up resistor from pulling current on the
    leg which is grounded.
    I will try to run this through SPICE to see how well it works. (you
    don't happen to have a spice model for this handy?)
    Thanks,
    Ron
     
  10. Fred Bloggs

    Fred Bloggs Guest

    If static discharge through the switch is your main concern then you can
    select a switch designed for this purpose, the vast majority of panel
    mount small signal stuff intended for applications like this protect
    against ridiculously large static voltage discharge making it onto the
    switch circuit terminals; that is just the first line of defense, the HC
    family will take care of the non-existent residuals. And, nope, did not
    run it through SPICE.
     
  11. If you want to be beastly about it, use cross-coupled inverters and
    forget the resistors entirely.
    Best regards,
    Spehro Pefhany
     
  12. Fred Bloggs

    Fred Bloggs Guest

    LOL- heck why not...
     
  13. usao

    usao Guest

    I think that low-power consumption is more important to me.
    I think the short spike in current will not be a problem, since the
    nand gates will flip-flop to match the input state of the switch very
    quickly.
    I was more concerned about some of the other more common circuits
    where you have a resistor between Vcc and Gnd which is constantly
    draining power.
    Your solution only has a very short spike but then it's neutral and
    shouldn't have any current through the resistor, as long as the gate
    output is at the rail voltage.
    Ron
     
  14. John Larkin

    John Larkin Guest

    Or milliseconds. Don't do that.

    But in real life, it will be high or low. While the switch is in
    mid-air, circuit capacitance will hold the node in its old state until
    the wiper hits the opposite side; then it will jump to the new state
    in nanoseconds.
    DC gate current is zero. The resistor will prevent nanosecond-range
    ringing from transmission-line effects on the run from the switch to
    the gate. I only mentioned it because sometimes folks get pickey
    around here.

    Please don't top post.

    John
     
  15. John Larkin

    John Larkin Guest


    John
     
  16. usao

    usao Guest

    I think ill stick to the SR FF with the resistors between ground and
    the output pins...
    Looks like im good to go. Thanks for all the help.
    Ron
     
  17. John Fields

    John Fields Guest

    ---
    These take less wire: ;)


    Vcc
    |
    O
    /
    +--O/ O-+
    | |
    | | \ | | \
    +--| >O--+--| >O--+
    | | / | / |
    +-------------------+


    +-------------------+
    | | \ | \ |
    +--| >O--+--| >O--+
    | | / | | /
    | |
    +--O\ O-+
    \
    O
    |
    GND
     
  18. Fred Bloggs

    Fred Bloggs Guest

    Flawed idea, susceptible to causing metastability at the receiver...
     
  19. John Larkin

    John Larkin Guest

    Yup, that's a nice one. And a cap to ground would harden it against
    stiff transient noise spikes, if present.

    John
     
  20. Arie

    Arie Guest

    "Fred Bloggs" ...
    I did measure the bounce time and pattern of a lot of different switches and
    relay contacts. Never saw any "first contact" below 100ns. That's enough to
    settle even a good old CD4000 buffer. Do you have you any data on the
    contrary?

    The circuit never failed me, even when using it to edge-trigger FF's or
    counters.

    Arie
     
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