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CMOS 4000 series Logic levels - Related to VDD

Discussion in 'Electronic Design' started by Klaus Vestergaard Kragelund, Nov 12, 2004.

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  1. Jim Thompson

    Jim Thompson Guest

    Yes ;-)

    See below.....




























    The threshold of CMOS logic is determined by the relative "strengths"
    of the opposing P- and N-channel devices.

    "Strength" of a device is determined by its "area" (W/L) and its
    type... N-type devices for a given area are generally 3-4 times
    "stronger than P-type devices.

    _CMOS_threshold_ logic parts (CD..., ..HC..., etc.) are generally
    designed so that threshold is at the mid-point of the supply. But
    specifications will say 30% to 70% of supply to account for processing
    variations, and to allow the sale of crap ;-)

    CMOS parts designed to interface to TTL will have a nominal threshold
    sized to 1.4V at the design power supply, but will vary
    percentage-wise with supply just as standard CMOS parts do.

    ...Jim Thompson
     
  2. Joerg

    Joerg Guest

    Hi Klaus,

    Jim explained it all, nothing to add from my side. One remark regarding
    the 4007. These are generally non-buffered devices and there is a U or
    UB behind the number. Level variation on these will be more pronounced
    since the inverter in this chip consists of just one pair and not three,
    meaning the gain is much lower and the threshold is much shallower than,
    for example, in an inverter of the CD4049BE. There is also an unbuffered
    version of the 4049.

    Regards, Joerg
     
  3. This phrasing is a bit misleading. The 4007 is a set of discrete
    transistors. The concept of buffered and unbufferd doesn't apply to
    individual transistors. You can connect up the 4007 as either a buffered
    or unbufferd inverter, but you can also use the transistors in any non
    digital way you like.

    Kevin Aylward

    http://www.anasoft.co.uk
    SuperSpice, a very affordable Mixed-Mode
    Windows Simulator with Schematic Capture,
    Waveform Display, FFT's and Filter Design.
     
  4. Joerg

    Joerg Guest

    Hi Kevin,
    That's right, it is a collection of FETs. However, the last stage (pins
    10 and 12) is configured as an unbuffered inverter except that the
    supplies are piped out. But the substrate doesn't allow much leeway
    there. You can make a unbuffered inverter from it but that would gobble
    up the whole chip for just one inverter.

    If I had a Christmas wish it would be a similar device in the 74HC
    series :) Well, until then it's the SD5400.

    Regards, Joerg
     
  5. Jim Thompson

    Jim Thompson Guest

    74HC4007 exists, though I couldn't locate a data sheet.....

    http://www.hkinventory.com/public/O...&SearchID=&crit3=&crit4=0&searchPN=&datecode=



    ...Jim Thompson
     
  6. Joerg

    Joerg Guest

    Hi Jim,
    I am not sure that this isn't a typo. The source they state is Ohm
    Electronics, which afaik is a sales organization in the UK. I might be
    wrong though. Thing is, the major parts distributors in the US don't
    have any. That usually means it is either unobtainium or a very slow
    selling part.

    Regards, Joerg
     
  7. Genome

    Genome Guest

  8. Joerg

    Joerg Guest

    Hi Guy,

    Thanks. At least the Philips HC family guide specifies quiescent current
    for analog use per unit load. They only state typical values but the
    min-max could be calculated from there using the min-max output current
    spread.

    The trick with analog usage is not to let it sit in the middle for bias
    but veer towards VCC or GND a bit. GND is mostly the more practical side
    to veer to. When staying in the triode region on either side the
    quiescent current can become quite minimal. If biased in the center the
    circuit would become a real "watt guzzler".

    Regards, Joerg
     
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