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clock generator

Discussion in 'Electronic Design' started by jason, Jul 5, 2005.

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  1. jason

    jason Guest

    Hello All

    Anyone can share the idea of designer a clock generator using cmos PLL
    technology?
    Do share with me any good link or material on this topic from basics to
    advanced level.
    Thank you

    rgds and thanks
    Jason
     
  2. John Fields

    John Fields Guest

     
  3. Boki

    Boki Guest

    Clock generator => VCO => PLL

    inverse?

    I don't understand...

    Best regards,
    Boki.
     
  4. jason

    jason Guest

    Hi All

    It is a kind of clock generator that make use of PLL or DPLL(mixture
    ofanalog and digital circuit) . The aim is to investigate the jitter
    and also skew when load , temperature and power supply is varying,
    Anyone know of such a reference?
    Kindly help

    thank you
    jason
     
  5. Boki

    Boki Guest

    so you have to inverse it to see that?
    Still not understand..

    Best regards,
    Boki.
     
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