P
[email protected]
- Jan 1, 1970
- 0
Hi all,
I want to implement a clock extraction circuit from data at 300 Mbps.
What i wanted to know is that is it really feasible in FPGA's( CYCLONE
II).
Is any reference design available on clock extraction circiuit.
Thanks in advance
Regards,
Praveen
I want to implement a clock extraction circuit from data at 300 Mbps.
What i wanted to know is that is it really feasible in FPGA's( CYCLONE
II).
Is any reference design available on clock extraction circiuit.
Thanks in advance
Regards,
Praveen