# Clock divider by 3 with 50% duty cycle?

Discussion in 'Electronic Basics' started by Davy, Oct 17, 2005.

1. ### DavyGuest

Hi all,

How to Build a Clock divider by 3 with 50% duty cycle?
Input and output are listed below.

Clkin
__--__--__--__--__--__--
Clkout
______------______------

Any suggestions will be appreciated!
Best regards,
Davy

2. ### PeteSGuest

One way to do this is to multiply the clock first (so the clock rate is
an even multiple of your desired divided clock) and then divide it back
down.

There are a number of methods - rate multipliers, for instance.
Depending on the clock speed and jitter constraints, you might use a
single chip PLL (Cypress makes some very nice ones).

Cheers

PeteS

3. ### Clifford HeathGuest

You design the state machine that your lecturer intended
you to design, or else you choose to learn nothing by
Googling for it. Good luck getting a job if you always
choose the latter path - you'll need it.

Hint: The state machine produces output transitions on
edges in alternating directions.

Clifford Heath.

4. ### deloGuest

use a toggle flip flop that toggle one time on rising one time on fall ( an
exor between output and clock
line ??? only a guess....).
bye
delo

5. ### M.RandelzhoferGuest

see:

http://www.xilinx.com/xcell/xl33/xl33_30.pdf

or use a Xilinx coolrunner2 CPLD with coolclock option (triggers flipflops
on both edges).

MIKE

6. ### Winfield HillGuest

Davy wrote...
This topic comes up every now and then on s.e.d. Here's an
answer I gave seven years ago, along with some others.

First my 1997 post, which uses two types of flip flops, one with
positive-going clocking and one with negative-going clocking. I
suppose you could use one type of flip-flop with a clock inverter.

From: Winfield Hill ()
Subject: Re: Divide by 3 Clock
Date: 1997/04/14

Anson Chi Fung at says...
Since no one has answered, Anson, I will. We do have a
divide-by-3 circuit in our book (AoE fig 8.59), but it doesn't
meet your specific symmetrical square-wave waveform requirement.
To meet it, the output must change state on both rising and
falling clock edges (and of course, the input clock must be a
square wave).

I made a design with this feature - matching your waveforms, in
1979 for a wave recorder at Sea Data. I don't know if it was a
_minimum_ part design, since it employs 3 flip flops rather than
two, but it has an additional feature of starting at a proper
phase after a reset. I hope there aren't any transcription
errors in this ACSII drawing!

,---------------------- J Q ----- out
clk* --+------------------------------------ CLK*
| | gnd --- K Q* -,
| | R* |
| | | |
| .-------------+------------------------------'
| | | |_ res*-- S* |
| '- D Q --+___ NOR ------ D Q |
+--- CLK ,---- CLK |
| Q*--, | Q*---'
res* ------ R* '-------------- R*
'-----------------------'

The D flops can be a HC74 and the JK flop a HC107 section, etc.
You can also use a cPLD, if it allows an inverter before a
register clock, since the JK flop must clock on an opposite
phase from the D flop.

Well, lunch hour is over - back to work! Let me know if this is
helpful, or if you come up with a better circuit.
-------------------------

From: (Jeroen Belleman)
Organization: CERN, European Laboratory for Particle Physics

The following equations describe a divide-by-three circuit which
will have a 50% duty cycle output, provided the clock also has
50% duty cycle, exactly as in the diagram above. Signal 'A' is
your output. '+' is OR and '&' is AND. '/' is inversion.

A = Ck & A + Ck & B + /Ck & A & C;
B = Ck & B + /A & B + /Ck & /A & C;
C = /A & C + A & B + Ck & /A + /Ck & C;

That's about twelve gates or so, not counting the inversions, and
no explicit flip-flops. There's a bit of redundancy in some
equations. You figure out where and why.
------

From: (Sam Goldwasser)

Here is one that I think will work using JK flip flops positive edge
triggered. My recollection was hazy and I had to rederive it.

+------+ +------+
+ ---| J Q |---+----| J Q |--+----> Divide by 3 out
+-|> | | +-|> | |
+ -|-| K Q'| +--|-| K Q'| |
_____ | +------+ | +------+ |
CLK >--| | | | |
| XOR |--+---------------+ |
+-|_____| |
| |
+--------------------------------------+

By inverting the clock on each transition of the output, this circuit
effectively removes two half periods from the divide by 4 circuit which
this would be without the XOR. Assuming the two flip flops come from
the same IC (meaning the propogation delays are reasonably well matched),
the output will be symmetric and the circuit is glitch and hazard free.

From: Winfield Hill ()
Subject: Re: Divide by 3 Clock
Newsgroups: sci.electronics.design
Date: 1997/04/15

That reminds me of the timeworn phrase, "That's idea's so-oooo crazy, it
just might work!" As a fan of XOR gates, I remember thinking of an XOR
approach when I worked on this 20 years ago, but was nervous about the
glitch factor when playing with the input to an edge-sensitive flop.

Analyzing the circuit now, it looks pretty good. It even has the "start
after three half-cycles" phase reset feature of my more complicated
circuit. Sure, the XOR gate output makes an alarming "runt" clock pulse
at every output transition, but its length is 2 propagation delays and
should reliably fire both flops.
--
Winfield Hill _/_/_/ _/_/_/_/
The Rowland Institute for Science _/ _/ _/_/ _/
Cambridge, MA USA 02142-1297 _/_/_/_/ _/ _/ _/_/_/
_/ _/ _/ _/ _/
http://www.artofelectronics.com/ _/ _/ _/_/ _/_/_/_/

From: Aroosh R. Elahi ()
Subject: Re: Divide by 3 Clock
Newsgroups: sci.electronics.design
Date: 1997/04/16

You don't get glitches and hazards in synchronous ccts.!

Aroosh R. Elahi

Faculty of Engineering, Carleton University

From: Sam Goldwasser ()
Subject: Re: Divide by 3 Clock
Newsgroups: sci.electronics.design
Date: 1997/04/16

Since the clock passes through an XOR, both are possible but this
implementation should not have them.

Glitches might occur if the clock were forced to change multiple times
based on feedback terms. This might result in one or more outputs going
through two transitions very quickly. Also note that textbook descriptions
are fine but in the real world, you have unequal propogation delays and other
effects which can really mess up your entire day! .

--- sam : Sci.Electronics.Repair FAQ: http://www.paranoia.com/~filipg/REPAIR/

-----------------
From: "Myron Loewen" <>

If you have not yet been rushed into a solution, you may consider the
following 50% duty cycle /3 with only 2 D flip flops and an XOR gate.
It creates the output CLK from the input CLK as you indicated.

.. Input CLK ---->
.. XOR >----> CLK D <-|
.. |--> FF1 |
.. | |-< Q /Q >-|
.. | |
.. | |
.. | |-> CLK D <-|
.. | FF2 |
.. |------------< Q /Q >-|
.. |
.. |-------------------------> Output CLK

Myron Loewen, Design Engineer, Norscan Instruments

8. ### Jim ThompsonGuest

See "DivideBy2p5.pdf" on the S.E.D/Schematics page of my website for
the basics.

(You create a reliable trigger/clock on both edges of the incoming
signal.)

You just need to rearrange the decoding to get div3 instead of div2.5

...Jim Thompson

9. ### Jim ThompsonGuest

See...

Newsgroups: alt.binaries.schematics.electronic
Subject: Re: Clock divider by 3 with 50% duty cycle? (From S.E.D) -
Div3-Symmetric.pdf
Message-ID: <>

...Jim Thompson

10. ### Jasen BettsGuest

If the clock is a fixed frequency just feed it through a resistor
into a suitably sensitive part of an astable multivibrator
tuned to approximately the right output frequency.

for example.

-+- VCC
|
|
.----------[RX]---}----------.
| | |
| +--------+ |
| | | |
| | . . . .|. . . . |
| | . VCC(8) . |
| | . . |
| +--RES(4) OUT(3)----+---
| . 555 . out
|\ +-[100K]-+--TH(6) DIS(7)--
in | \ | | . .
-----| >O---(-[470K]-+--TR(2) CV(5)--
| / | . .
|/ ----- . GND(1) .
----- . . . .|. . . .
| CX |
| |
`-----------------+--- GND

Bye.
Jasen

11. ### Guest

Jim Thompson skrev:
And to get 50/50 the input clock also needs to be 50/50

-Lasse

12. ### Jim ThompsonGuest

Yep, That's why these "odd-clock" schemes are not often used in
critical applications.

...Jim Thompson