# Clock-dependent signal question

Discussion in 'Electronic Basics' started by Rikard Bosnjakovic, May 17, 2006.

1. ### Rikard BosnjakovicGuest

In a project, i have a clock-signal and two other signals (A and B). A and
B are the opposite of each other - when A is HI, B is LO, and vice versa.
This project has no microcontroller (or similiar) involved, I have to
solve it using basic logic components (gates/diodes, TTL/DTL, etc).

Here's the problem:

I want signal A to depend on the clock. At each edge-fall of the clock, A
should change it's state. I.e., when clock goes from LO->HI, nothing
happens. When clock goes from HI->LO, A goes from HI->LO or LO->HI,
depending on its current value.

The value of B is the inverted value of A, so there's no headache for me
there, but since I haven't worked with signal transitions before I cannot
seem to find a way for signal A to depend on the clock as described.

I'm pretty much clueless and I'd be grateful for any hints of how I might
find a way to solve this trickster.

2. ### Greg NeillGuest

Take a look at the gate design for a D-type flip-flop.
Then do something clever with the Q' output.

3. ### ChrisGuest

Hi, Rikard. I think you're looking for what's called a Toggle
flip-flop, sometimes called a "T"-FF.

Given a clock, you want every negative transition of the clock to
result in the output of the flip-flop to change state. Also, you'd
like the T-FF to have complementary outputs, one being the inverse of
the other.

You can make a T-FF out of a D-type FF (data-type flip-flop) by feeding
the inverting output back into the data input. That way, every time it
clocks, it changes state.

Unfortunately, I believe all of the commonly available data-type flip
flops have transition on the positive-going transition of the clock.
So, you can easily do your logic function with half of a CD4013 (dual
D-type FF) and an inverter gate, like this (view in fixed font or M\$

|
|
| .------------------.
| | VCC |
| | + |
| | | |
| | .------o-----. |
| | | Vdd | |
| '--o D Q o--)---A
| | | |
| | 1/2 CD4013| |
| CLK IN|\ | | |
| o--| >O---o CLK Q'o--o---B
| |/ | |
| |Reset |
| | Set Vss |
| '--o--o---o--'
| | | |
| ====== ===
| GNDGND GND
|
|
(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)

http://www.onsemi.com/pub/Collateral/MC14013B-D.PDF

Hope this is of help. If not, feel free to post again.

Good luck
Chris

4. ### BanGuest

I can not make your homework for you, but I will give you a hint. you need 2
static FFs in series, where the clock for the second is inverted. this will
need 9 Nand gates and is called Master-Slave RS-FF. The output is fed back
to the input. The JK-MS-FF has this connection already wired and you have to
tie the J and K high.
This basic cell is twice in the 74112. It is used to make a frequency
divider or in binary counters. You could also use the first stage of a 7493,
which is an asynchronuos 4-bit counter.
How comes you pretend to have studied Computer Science and do not know this?

5. ### Rikard BosnjakovicGuest

This is not homework, I'm not attending school. I've setup a problem to
solve to be able to extend my abilities in sequential logic. I'm trying to
simulate a crossroad with traffic signs. This way - for me - is the best
way to learn new tricks. Just because you're too naive to make your own
problems to solve it doesn't mean everybody's like that.

I will disregard your pompous tone, this time. Don't throw crap on people

CS in Sweden does not incorporate any hardware-related material, but a lot
of software pragmatism. Think of it as software engineering without any
hardware.

6. ### BanGuest

Electrical Engineering, Chalmers university of Technology, 2005-
So your web page is a lie.
Well I gave you also some nice part numbers and an explanation. Just get
lost when you cannot appreciate any help.

7. ### Rikard BosnjakovicGuest

Your "help" was overwhelmed with pompous, prejudiced and pointless crap.

8. ### Rikard BosnjakovicGuest

Chris wrote:

[snip]
Thank you Chris.

Using a flip-flop with an inverter makes sense, I think. I haven't used
any flip-flops yet so I guess I will play around a bit with them first to
get a better grip of how they work.

Off the shelf without any testing, I think that inverting the clock signal
before entering the flipflop would yield me the same result, won't it?
That is, a negative edge-trigger instead of a positive one. I think I will
test this along with your tip. Both will probably work, and I have a free
inverter-gate on my board so I don't have to clog up with more ICs.

9. ### Rich GriseGuest

He says, as he proceeds to do the kid's homework for him.
The word, "D flip-flop" comes to mind...

Cheers!
Rich

10. ### Rich GriseGuest

Yeah, so what? There's a lot of that around here.

Was it _accurate_?

And it's considered bad form to get snippy when receiving open-ended

Good Luck!
Rich

11. ### Rikard BosnjakovicGuest

Yep, and that was the golden nugget in this case. Using a D-flipflop
together with Chris' tip about feedbacking Q inverted into D-input solved
this little afternoon project.

http://bos.hack.org/tmp/cache/traffic_light.pdf

The reason I built this pretty pointless stuff was because I wanted to try
to implement an own made timing diagram which I drew yesterday. Instead of
having a rapid clock and buffer/count the transitions, I used a 7 second
period clock that immediately feeds the yellow light. The red and green
light are switched at every 7 second (where the clock edge drop occur).

Red: HI 7 secs, LO 7 secs, repeat
Yellow: LO 5 secs, HI 2 secs, repeat
Green: LO 7 secs, HI 7 secs, repeat

This circuit will (un)fortunately not replace the existing lights in my
town, but it was fun to implement a circuit out of a timing diagram.