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Discussion in 'Electronics Homework Help' started by bhuvanesh, Sep 19, 2014.

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  1. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    Do u think the circuit is correct.See from the circuit if the complimented output of 1st f//f is 1 and second normal output is 0.Then whats the one of the input of and gate.The two outputs wires are merged is that correct?
     

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    Last edited by a moderator: Sep 20, 2014
  2. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    If you tell us what the circuit is supposed to do, we might be able to tell you whether it's correct or not...
     
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  3. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    mod 5 down counter
     
  4. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    in mod 5 down counter at 5th clock pulse whether circuit resets to 000 or 111?
     
  5. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    OK. First you need to mark the outputs on the drawing. It may seem obvious to you that AQ, BQ and CQ are bits 0, 1 and 2 of the output, but that's no excuse for not showing this information explicitly. You also need to indicate whether the preset inputs are active high or active low. Without knowing this information, you can't define the circuit properly.

    Then draw up a table headed up with all of the nodes in the circuit (apart from the clock, which can be assumed to be idle). I started making a list of these nodes and very quickly noticed that two flip-flop outputs are shorted together, which is definitely an error. You need to figure out what went wrong there and fix it before you can analyse the circuit.

    Then calculate the circuit's behaviour on lines in the table. For each possible output value, work out the states of all the nodes and write them in on one line. Then work out what will happen when a clock pulse is received, and write the new states of all the nodes (after the clock pulse) on the next line.

    Then by comparing the behaviour to the required behaviour for a mod 5 down-counter it should be pretty clear whether the circuit will work or not.
     
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  6. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    Modulo 5 means that the valid output values are 0, 1, 2, 3, and 4. Since it's a down-counter, those numbers appear in reverse order. So the output pattern should be 000 (0); 100 (4); 011 (3); 010 (2); 001 (1); 000 (0); 100 (4); 011 (3); 010 (2); 001 (1); 000 (0) etc. Do you agree?
     
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  7. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    no i dont agree pattern should start from 7(111) then 6 5 4 3 2 and resets.right?
     
    Last edited: Sep 20, 2014
  8. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    So what should the whole pattern be? What comes after 7? Then what? Can you list the numbers, in sequence, the way I did?
     
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  9. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    111(its in initial state),at 1st clock pulse 6(011),5,4,3,2(010),0(000),7(111) the goes on
     
  10. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    Try again using only decimal numbers. Do you mean 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, ...? What does "mod 5" mean to you?
     
  11. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    mod 5 mean the one that resets at 5th clock pulse.my sequence is 7,6,5,4,3,0,7,6,5,4,3,0.is that right?
     
  12. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    Mod 5 means that there are five possible output values, and because it's a down-counter, they will be generated in descending order. Specifically, mod 5 means "the remainder after division by 5". If you divide any number by 5 and look at the remainder, it will always be either 0, 1, 2, 3 or 4. So those are the values I would expect to see from the counter. So I would expect the output sequence to be 4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, ... Does that make sense?

    Have you fixed the problem with the two flip-flop outputs shorted together?
     
  13. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    yes
    i agree with u at the same time remember 7/5 gives 2 as u say.now say whether my statement is right or wrong
    1)no of states =mod number
    2)mod 5 so 5 states
    3)in up counter the counter resets itself at particular sequence to 0 and in down counter presets to 1
    5) states so 3 f/f which are initally at 111 and sequence goes by 6543 again 76543

    the counter restes (0) pt preset(1) but according to your statement its changing to 001(4).how is that possible

    please help me to find where i am mistaking
     
  14. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    I have no idea what you mean by that. Do you mean 7 - 5 = 2? Because 7/5 is 1.4. And in any case, a 3-bit counter has eight states, not seven.
    Right.
    Right.
    In an up-counter, when the count tries to increase from the maximum count, it resets to 0, yes.
    In a down-counter, when the count tries to go below zero, it "presets" to the maximum value.
    That's not how I see it. Strictly speaking, as long as there are five different states and the numbers occur in decreasing order with no gaps, you could argue that it counts "mod 5". For example, 7,6,5,4,3,7,6,5,4,3,7,6... could arguably be described as "mod 5" but strictly speaking, "mod 5" means "remainder after division by 5", and the remainder after division by 5 can only be 0, 1, 2, 3 or 4. So I would expect the counter to count 4,3,2,1,0,4,3,2,1,0,4,3...
    I don't understand your question.
     
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  15. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    please show me mod 5 down counter.please
     
  16. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    I don't understand what you want. Do you want a schematic for a mod 5 down counter? You can probably find one using Google.
     
  17. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    i understood something wrong in textbook.i come after detail study .Thanks sir
     
  18. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    OK. and there's no need to call me sir :)
     
  19. bhuvanesh

    bhuvanesh

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    Aug 29, 2013
    i google as mod 5 down counter .i didnt get that .could u suggest me any good page to see mod N down counter
     
  20. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

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    I couldn't find a modulo N down-counter but I did find two good articles that explain enough for you to be able to design one.

    First, Tony R. Kuphaldt's excellent lessons at http://www.allaboutcircuits.com/vol_4/chpt_11/3.html. This section on digital logic is also available for download as http://www.allaboutcircuits.com/pdf/DIGI.pdf. You should definitely get this PDF. It's well-written and you can learn a lot from it.

    Start reading with section 11.3 on page 332. There's a 4-bit down-counter design on page 336. If you've read and understood the text, you should be able to figure out how to convert this to a 3-bit mod 5 down-counter.

    Second, there's an article at https://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html that covers the same topics, which may be helpful to you as well.
     
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