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CD4013 Vdd?

Discussion in 'Electronic Design' started by Mark Jones, Nov 9, 2004.

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  1. Mark Jones

    Mark Jones Guest

  2. Jim Thompson

    Jim Thompson Guest

    Probably. All you can do is try it. My experience is that CMOS will
    usually operate right down to a supply equal to two thresholds, or
    about 1.5V. It _will_ be _slow_.

    ...Jim Thompson
     
  3. Andrew Holme

    Andrew Holme Guest

    It's not gauranteed. The small print below the absolute maximum ratings
    says -

    This is a stress rating only and functional operation of the device at these
    or any other conditions above those indicated in the operational sections of
    this specification is not implied.
     
  4. Don't expect any two to operate similarly, though you might find some
    that work. I suggest you start with a chip based on a lower voltage
    process like the HC, HCT, ACT, AHC family.
     
  5. Jim Thompson

    Jim Thompson Guest

    That's the ticket, just get a 74ALVC74, although I'm sure that the
    74HC74 design I reworked for ON Semi will work at 2V.

    ...Jim Thompson
     
  6. Tim Wescott

    Tim Wescott Guest

    The only problem being that if you get it into production and it doesn't
    work the way your samples did the manufacturer will say "tough s---,
    you're running it out of spec".
     
  7. Jim Thompson

    Jim Thompson Guest

    Of course. However I doubt that anyone inquiring about a 4013 could
    have production in mind ;-)

    ...Jim Thompson
     
  8. Ken Smith

    Ken Smith Guest

    Something from my memory raises a danger flag.

    The CD4013 uses "analog switches" to route the signals to create its
    flip-flops.
     
  9. Ken Smith

    Ken Smith Guest

    It makes a good device for rememebering whether the "power is on" or not
    in a system that leaves some of its logic always powered. The CD4XXX
    stuff draws almost nothing. I know of at least one product with a
    membrane keypad that powers on by flipping a CD4013 flip-flop.

    Someday I hope some bright company sees this sort of application and makes
    a super low power, wide VCC range highish density CPLD or FPGA.

    BTW: What I'm designing now draws lots of power so right now, I don't
    need that.
     
  10. Ken Smith

    Ken Smith Guest

    No-one else said it so "just use a PIC". They work down to 2.0V at slow
    clock speeds.

    If you care about the low static Idd, most HC parts are OK in that regard
    but you have to spec. the suppliers because others aren't.
     
  11. Jim Thompson

    Jim Thompson Guest

    Yep. But they be P- and N-types in parallel, thus my 2*VT rule still
    applies.

    ...Jim Thompson
     
  12. Ken Smith

    Ken Smith Guest

    Yes, now that I've though about it I remember that the analog switches are
    driven by inverters and drive inverters. This makes it no worse than a
    NAND or NOR driving another gate. There are two devices (N or P) in
    series doing the ull UP or DOWN.
     
  13. Tim Wescott

    Tim Wescott Guest

    The 4013 _is_ a MOSFET design, so there's no free lunch there. There
    are 3.3V "Logic" MOSFETs out there, so there's hope.

    Use a P-channel MOSFET to turn it on, with an NPN "logic" transistor
    from the PIC to keep it on. Connect the gate of the MOSFET to the
    transistor collector and the switch. Make sure to scan the state of the
    switch on power up, or delay for a bit when you turn on -- I've had
    power supply decoupling caps bounce up in voltage when the current drain
    is removed, turning the uP back on.
     
  14. Martin Brown

    Martin Brown Guest

    Dunno, but you can get the consumption of a 16xxx down to around 10-15uA
    at 32kHz on 3v without trying too hard simply by disabling all
    unnecessary bits - and much less with cunning use of sleep mode.

    Regards,
     
  15. Ken Smith

    Ken Smith Guest



    How about this to get more gate drive?:

    Buffer
    !\
    -----! >---+--------->!-------+------+------------ Mosfetgate
    !/ / ! !
    \ --- /
    / --- \
    ! !\ ! /
    +----! >------------ !
    ! !/ GND
     
  16. john jardine

    john jardine Guest

    Neat idea that!.
    Like the way it can extend as a ladder form.
    regards
    john
     
  17. Tim Shoppa

    Tim Shoppa Guest

    Especially with clocked flip-flops going into a region where
    rise and fall times are glacially slow is a bad thing.

    It's not so bad if you can do your function without a clock line
    (a set-reset flip flop).

    There are D-type flip-flops that work fine under 2V; the 74AUC74
    for example (if you know anywhere to buy it...) has versions that
    are supposed to go down to 0.8V.

    Tim.
     
  18. Guy Macon

    Guy Macon Guest

    If possible, feed those slow rising/falling signals into a
    schmitt trigger and use the output of that to clock your
    flip-flop. You can use a logic gate that already has a
    schmitt trigger on the input, or you can make one with a
    comparator or opamp using positive feedback.
     
  19. Joerg

    Joerg Guest

    Hi Mark,

    It looks like you are the OP (can't see the whole thread). Have you
    considered the 74HC series? It is meant to operate between 2V and 6V so
    it may be a nice fit here. They are much cheaper than newer very low
    voltage logic and sometimes cost even less than CD4000 chips. Also, I'd
    look into a Schmitt device here.

    Regards, Joerg
     
  20. N. Thornton

    N. Thornton Guest

    Or a logic gate with pfb

    NT
     
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