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Cascading shift registers

Discussion in 'Electronic Basics' started by valentin tihomirov, Jan 13, 2005.

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  1. Call me a dumb but I cannot find any app notes on that. Are there any clock
    implications, is it the major concern? When many registers hang on the same
    clock line the open-collector controlled by degrades very quickly resulting
    in too slow slope. I have tried NAND logic and it seems to work well. But
    the clocking problems are hard-to-debug (they may appear occasionally) so i
    want to be absolutely sure about the proper clock distribution. Should any
    "specially designed drivers", schmidt triggers be used to rectify the signal
    or the conventional logic gates, transistors are just good for this purpose?
    What are the typical circuits?
  2. Leon Heller

    Leon Heller Guest

    You should be OK until you exceed the fanout of the clock. It will be
    dependent on the clock speed, as well.

  3. Tim Shoppa

    Tim Shoppa Guest

    The problem is usually not the individual parts but the whole clock
    distribution topology.

    In some cases putting faster stiffer drivers on the lines will let you
    do better with a questionable topology... but it's still a poor design.

    Capacitive loading can also depend on construction technique as well as
    topology. You mention "open collector", if you are using pull-up
    resistors this pretty much guarantees capacitive loading slowing down
    your clock transitions if you clock on the rising edge, and you'll
    likely end up with problems of false triggering on a slow rising edge
    even if you're clocking on falling edges.

    The "classic" way of dealing with all this is to use equal-length
    transmission lines and proper receivers and drivers for all clocks.
  4. John Larkin

    John Larkin Guest

    A shift register needs a fast clock edge to shift reliably; the clock
    risetime should be comparable, or better less than, the propagation
    delay of the flipflops inside the register. Any slow clock should be
    cleaned up with a schmitt or something.

    Between separate shift register chips, clock skew is fatal. If skew is
    possible, add some delay (RC or some gate delays) between the Qn
    output of each chip and the Din of the next, more delay than the max
    possible clock skew.

  5. krw

    krw Guest

    Another "trick" is to route the clocks from the Qn (last FF) towards
    the Q0 (first FF).
  6. I have routed clocks the opposite direction of the data shift, with a
    clock buffer between each register chip, so the propagation delays
    occurred in opposite directions. Only two loads on each clock (one
    register and one clock buffer).
  7. keith

    keith Guest

    That's fine if the clock nets are heavily loaded, though I propose that
    it's not necessary to do both, since he clock buffers add delay.
  8. If skew is possible, add some delay (RC or some gate delays)

    How do I know this in advance?
  9. Call me a dumb but I cannot find any app notes on that. Are there any clock
    1. The SRs will need a clear clock. This can easily be solved by
    adding a ST buffer bufore each clock input. Note that some SRs have a
    ST input.

    2. When SRs are cascaded clock skew can be a big problem. The IMHO
    best way to avoid this is using SRs with a delayed output, like the

    Wouter van Ooijen

    -- ------------------------------------
    Webshop for PICs and other electronics
    Teacher electronics and informatics
  10. John Larkin

    John Larkin Guest

    If the clock has a clean, fast rise time (and an open-collector won't)
    and is routed to a small number of chips using short traces, it's
    probably OK. Generally a logic level generated by a given logic family
    is adequare to clock a small number (say, six?) devices of that same
    logic family. Expect trouble splitting a simplistic shift register
    across boards or scattering a lot of stages about a single board.

    That's the basics. The details get into PCB trace impedances,
    setup/hold time specs, signal integrity, stuff like that, the things
    digital design engineers deal with.

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