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Capacitance on PIC I/O line

Discussion in 'General Electronics Discussion' started by Rajinder, Nov 27, 2018.

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  1. Rajinder


    Jan 30, 2016
    I wanted to ask a question regarding capacitance on the input of a PIC I/O line. Why is this undesirable?

    Is it because if we get a voltage rising quickly then we will get a sharp rise in current due to the capacitance? Hence we must keep try and keep the capacitance as a low value?

    Also what methods can we employ to keep this as a low value? How does this effect decoupling capacitors.

    Thanks in advance.
  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    Jan 21, 2010
    Capacitance on the I/O lines will affect rise and fall times, and eventually the maximum frequency. It has nothing to do with bypass capacitors. Minimising the length of I/O lines will keep parasitic capacitance and inductance low.
  3. hevans1944

    hevans1944 Hop - AC8NS

    Jun 21, 2012
    This is the best overall general advice you will get regarding I/O lines.

    However, I/O lines on PICs have characteristics that depend on whether they are programmed as digital or as analog lines. Additional capacitance on digital I/O is almost always undesirable because it slows the rise time and fall time of digital edge transitions. This in turn leads to other undesirable behavior, such as timing errors and even missed transition-events (bandwidth limitation). It is best to avoid adding any additional capacitance to digital I/O lines by carefully following Steve's recommendation. Circuit board layout is important here.

    PIC I/O programmed as analog inputs are sometimes benefited by an RC circuit attached near the appropriate pin, the time constant being chosen to roll off the high-frequency response of the input to minimize analog signal noise and prevent "false positives" in comparator applications. An RC network (series input resistor plus a shunt capacitor) will attenuate fast-changing analog-to-digital converter inputs, which can lead to inaccurate conversions for rapidly changing analog inputs, but with decreasing digitization noise. Such "signal conditioning" should be performed in earlier stages, where it can be better controlled, with the A-to-D input driven from a low-impedance, low-noise, voltage source. Placing an RC network at the input to the A-to-D is a "band aid" that sometimes works.

    Long circuit paths are invariably associated with increased parasitic capacitance and inductance. While a few additional picofarads, or a few extra nanohenries, here and there may not seem like much, they are not part of an intentional design. It is good engineering practice to minimize such parasitic capacitances and inductances.

    Back in the day, some people would twist short lengths of insulated wire together to make a "gimmick" component and then prune the gimmick to such a length that it served its intended purpose. While this generally "worked" for one-off projects, it was not good engineering practice because it lacked repeatability.
  4. Rajinder


    Jan 30, 2016
    Thanks for your advice guys, much appreciated. Is excess current draw through the capacitor when the voltage changes suddenly also a problem associated with capacitors.
  5. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    Jan 21, 2010
    No, it is a feature of capacitors
    hevans1944 likes this.
  6. BobK


    Jan 5, 2010
    If you are worried about an input drawing an enormous current and blowing out your signal source, no, this is not a problem. The capacitance is tiny and the current would be drawn for only nanoseconds. The capacitance of the output source would generally supply all the current needed. You do not have to do anything to limit current into a PIC input. If you see someone putting a resistor in series with an input, it is there to protect against a software bug that makes the input an output.

    hevans1944 and (*steve*) like this.
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