Connect with us

cadence allegro design reuse problem

Discussion in 'General Electronics Discussion' started by adeel abid, Nov 5, 2013.

Scroll to continue with content
  1. adeel abid

    adeel abid

    12
    0
    Sep 4, 2012
    i am having problem in design reuse with allegro. i am using hierarchical design in which two external designs are instantiated twice.(total modules = 4(M1,M2,M3,M4)) but after all steps given in capture tutorial and final netlist generation when allegro window opens, it has all the four modules but in M1 half of the some nets(after via) has the net_name of M2 and same is the case with M1. the same is repeated with M3 and M4. please advise what is going wrong? i am using ver 16.0
     
  2. adeel abid

    adeel abid

    12
    0
    Sep 4, 2012
    Has anyone used the feature of design reuse by making .mdd file in allegro through orcad capture? please let me know the stepwise process.

    Adeel
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-