# Building a sunset dimmer

Discussion in 'General Electronics Discussion' started by DontLetTheSmokeOut, Nov 18, 2012.

1. ### DontLetTheSmokeOut

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Aug 18, 2012
I'm trying to simulate a circuit that dims a 12V lamp over a 1.5hour time period. I use LTSpice as my simulator.

I need to do the simulation over about 7000 seconds. I set this with a max step size of 1s, but for some reason LTSpice thinks it needs a step size in the us range. It will take days to co that simulation and would be so large as to be unusable.

How do I get the simulator to pick a "better" min step size?

The circuit I'm working from is here:
http://www.bowdenshobbycircuits.info/page6.htm#eyes6.gif

Also open to other ideas on how to do this.

thanks,
dave

2. ### Harald KappModeratorModerator

10,793
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Nov 17, 2011
The "step size" in any SPICE based simulator is the smallest increment that leads to usable results (acceptable error).
Keep in mind that a simulator running on a digital computer has to approximate the continous time (and analog values) by discrete (digital) values. And it has to use numerical procedures to approximate the ideal functions (integration, differentiation etc.) It can do this approximation only by making the time step so small that the resulting error is within some acceptable limit. That is why you can tweak so many simulation parameters.
Setting the step size to 1s doesn't help the simulator because it has to evaluate the behaviour within that intervall, too. Therefore the step size is automatically reduced until the error is within limits.

I guess you're trying to simulate the "Automatic 12 Volt Lamp Fader" from the page you linked to. If so, I suggest you reduce the 100µF capacitor (the timing element for the fading) to 1µF and reduce the simulation time by the same factor from 7000s to 70s. Or use 100nF and 7s.
Now the fading is 100 times (or 1000 times) faster, but you can mentally scale the time by the same factor to compare the simulation result with your expectations.

Another approach would be to split the circuit in two parts:
- the fader (top 2 OpAmps)
- the pulse generator (lower OpAmp)
Simulate both parts independently. Neither do you need the pulse generator to check the function oft he fader, nor do you need the fader (and aslo not the long simulation time) to check the function of the pulse generator.
Once both parts are running as expected, you can combine the circuits and make one last (long) simulation.

Harald

3. ### DontLetTheSmokeOut

17
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Aug 18, 2012
OK that is what I suspected. Sorry it's been a very long time since I've done spice

So I have it starting to run now but get the error:
Analysis: Time step too small; time =xxx, timestep = xxxe-15: trouble with 1n4002-instance d1. If I change the cap to make it simulate faster, it just has issues with d1 sooner.

thanks,
dave

4. ### DontLetTheSmokeOut

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Aug 18, 2012
Not sure what is going wrong, so I've attached the spice files. Hopefully someone can tell me what I'm doing wrong.

thanks,
dave

5. ### DontLetTheSmokeOut

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Aug 18, 2012
Now with the file attached . . .

File size:
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6. ### DontLetTheSmokeOut

17
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Aug 18, 2012
It seems to be a limitation of the LM324 spice model I downloaded from LTSpice (the model is from National). If I swap it out for a LT6231 that comes with LTSpice it runs fine.

dave

7. ### Harald KappModeratorModerator

10,793
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Nov 17, 2011
Well,
those are just models...

8. ### DontLetTheSmokeOut

17
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Aug 18, 2012
OK this isn't working like I expected Maybe you can help explain why?

From my understanding R3 and C2 set the frequency of the output from U5, U7 then inverts and creates a square wave of the same frequency.

R6 and C3 create the reference voltage that U6 uses to vary the duty cycle of the NFET. As the duty cycle changes the light is dimmed until it turns off.

At least that is what I expected to see.

What I see is that the reference voltage created by R6 and C3 is not an ever increasing voltage, but it oscillates with the output of U6. The inN terminal of U6 is sinking/sourcing current C3. This means that eventually it stabilizes at a 50% duty cycle and never changes.

I don't know what D1 does and now wonder if I know how this should work at all.

Am I reading this wrong? Maybe the op amp model is wrong and should not be sourcing current to C3?

One thing I did to speed up the simulation was reduced the size of C3, lowering the R6*C3 time constant hoping to see a steeper voltage ramp for u6. It just hit the 50% duty cycle and started oscillating sooner.

thanks,
dave

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9. ### Harald KappModeratorModerator

10,793
2,435
Nov 17, 2011
Not exactly. U5 is an integrator. It integrates the input signal (output of U7) to generate a sawtooth wave. U7 therefore is part of the oscillator.

The LT6231 has an input bias current of up to 10µA. Compare this with the current through R6: 12µA. It is therefore possible that the input current of U6 influences the circuit noticeably.

Last not least D1 is meant to discharge C3 rapidly when the power is turned off.

: I'm sorry, I made a mistake: the simulation time is not determined by C2. You can reset the components of the oscillator circuit to their previous values. What is important is the R6*C3 time constant. Reduce R6 and C3 to reduce the dimming time.
Note that this will also seemingly alleviate the problem of U6s input current. However, if you build the real circuit using 1Meg*3300µF the problem will reappear. Especially since a 3300µF electrolytic capacitor contributes some leackage of its own.

Analog circuits with that long time constants are notoriously difficult. May I suggest you look into a microcontroller solution?

Harald

Last edited: Nov 19, 2012
10. ### (*steve*)¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥdModerator

25,448
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Jan 21, 2010
You might have better luck with a super-capacitor and a constant current discharge (say in the uA range). As long as you don't mind individually calibrating each circuit, and a +/- 20-50% variance in time is OK it might work.