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BUCK switching waveform ... problem

Discussion in 'Power Electronics' started by x1215, Apr 3, 2018.

  1. x1215

    x1215

    9
    1
    Oct 30, 2016
    I have a 5V to 1V bulk which is built in PMIC, the schematics diagram is as below picture
    [​IMG]
    I measure at the point LX, the waveform as below is wierd, I think it should be square waveform, but it is a little distored.
    [​IMG]
    Need help what is going on?
     
  2. Bluejets

    Bluejets

    3,532
    716
    Oct 5, 2014
    What is it like on the other side of the inductor?
     
  3. x1215

    x1215

    9
    1
    Oct 30, 2016
    @Bluejets
    Output voltage waveform is not good, due to sink current change fast.
    [​IMG]
     
  4. Bluejets

    Bluejets

    3,532
    716
    Oct 5, 2014
    So am I reading this correctly?

    You have a 26mv spike lasting 2.5usec?
    What is the load?
     
  5. x1215

    x1215

    9
    1
    Oct 30, 2016
    YES you are right.
    Load is CPU's V-CORE, current consumption MAX to 2A.
    Because I am not much familiar with DCDC buck, so I don't know if the LX signal is fine or not.
     
    Last edited: Apr 3, 2018
  6. duke37

    duke37

    5,254
    726
    Jan 9, 2011
    If Q1 turns on fully then the LX waveform should have a flat top at 5V.

    I thought that Q2 should have a diode across it to take the current while Q2 is turning on.
     
  7. WHONOES

    WHONOES

    734
    151
    May 20, 2017
    No, the waveforms shown are quite normal.
    The circuit shown is a Synchronous Rectifier type where the normal diode is replaced with Q2. Q2 would normally be on when Q1 is off.

    The output ripple can be caused by a number of things.
    • Parasitic capacitance of the inductor windings. This allows the fast edges of the switching waveform to partially bypass L.
    • Poor ESR of Cout. Large electrolytic types will exhibit this. Several smaller value types will help to mitigate it. A few 100n ceramic caps will also help.
    • Poor layout will also contribute. One of the main candidates here would be poor grounding. All the high current points should sum at one junction and not be daisy chained.
    • A lot of the rubbish on the output could be removed by the use of a high impedance Cylindrical Ferrite core on the output leads.
     
  8. BobK

    BobK

    7,645
    1,662
    Jan 5, 2010
    Is a load connected?

    Bob
     
  9. WHONOES

    WHONOES

    734
    151
    May 20, 2017
    Loading the output will make the ripple worse.
     
  10. BobK

    BobK

    7,645
    1,662
    Jan 5, 2010
    Some switchers do not work well with no load.

    Bob
     
  11. WHONOES

    WHONOES

    734
    151
    May 20, 2017
    I agree but, that generally affects their ability to regulate properly.
     
  12. x1215

    x1215

    9
    1
    Oct 30, 2016
    the output have a ARM V-CORE sink,I will try to put some 100nF first.
     
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