# Bowden's BCD clock circuit

Discussion in 'Electronic Basics' started by John Popelish, Apr 12, 2007.

1. ### John PopelishGuest

I'll take a shot.

The CD4040 is a binary counter that resets to all zeros out
with Q1 being the 1 bit, Q2 being the 2 bit, Q3 being the 4
bit, etc.

http://www.fairchildsemi.com/ds/CD/CD4040BC.pdf

The bottom NAND outputs a low when both inputs are high, and
these inputs are the 4 and 8 bits.

The upper NAND gate outputs a low when its two inputs are
high, and these bits are the 16 and 32 bits.

So starting at a reset, the first count that produces a low
from both gates at the same time happens at count
32+16+8+4=60. This low state is slightly delayed by an RC
filter and inverted to a high by the inverter. This rise
from low to high clocks the second counter every 60th line
cycle and also resets the counter back to zero before the
61st cycle occurs, so when it does, it is counted as 1 of
the next 60.

The duration of the second pulse is set by the time delay
between when the reset pulse is sent to the counter and how
long it takes for the disappearance of the 60 decode passing
through the RC filter. That is roughly a millisecond.

2. ### John PopelishGuest

What you call Q0 (and my data sheet calls Q1) is the 1 bit
of the count. So pins 6,5,3,2 are the count bits
representing 4,8,16 and 32. The counter is fed with AC
upstream of the rectifier.

3. ### John PopelishGuest

The one I posted a link to, has all Q values 1 higher than
this lovely picture.

4. ### GregGuest

I've decided to build a BCD clock and after searching for a circuit
I've decided on Bill Bowden's circuit.

http://ourworld.compuserve.com/homepages/Bill_Bowden/clock.htm

After examining the circuit, though, I'm curious about the circuit
giving a pulse every second. There are two NAND gates attached to the
4040 binary counter which then feed into an OR gate. Am I correct in
assuming that they should be feeding into AND gate to get a pulse
every second? As the circuit stands, I would think it's going to give
a pulse on 0.8 sec and on 0.2 sec, or two pulses per second.

I'm fairly weak on logic circuits so forgive the stupid question.

Greg

5. ### Lord GarthGuest

View in fixed width font.

4040
+---\/---+
1 -|Q11 Vdd|- 16
2 -|Q5 Q10|- 15
3 -|Q4 Q9|- 14
4 -|Q6 Q7|- 13
5 -|Q3 Q8|- 12
6 -|Q2 R|- 11
7 -|Q1 /CP|- 10
8 -|Vss Q0|- 9
+--------+

Pin 6, 5, 3, 2 are 8+16+32+64 which equals 120 as the divisor
so you'll get 1 pulse per second due to the full wave rectifier at
the power supply.

6. ### Lord GarthGuest

Check those Q weights again John....

7. ### John PopelishGuest

Yes. That is why I complimented its beauty.
Page 1 of:
http://www.fairchildsemi.com/ds/CD/CD4040BC.pdf

8. ### John PopelishGuest

Right. So the only way the output can go low is if both
inputs are low.
The 4+8 gate outputs a low during the counts of 12 through
15 (those counts all contain 12, plus, possibly some bits
representing values of 1 or 2). At a count of 16, bits
1,2,4,8 go low and bit 16 carries the total, so the 12
decode goes away (goes high) at that point.

Then at a count of 28, the 4 and 8 bit are both high, to add
to the 16 bit, so the 12 decide goes low again till the
count reaches 32, when all the lower bits reset, to be
replaced by the 32 bit.

The 12 decide goes low a third time when the total count
reaches 32 + 12 = 44, and stays low for 3 more counts
through 47. At count 48, the 16 and 32 bits carry the
total, and all lower bits are reset.

The 12 decoder goes low a 4th time when the count reaches
32 + 16 + 12 = 60, and at that point the whole counter is
forced to a reset count of zero, and the whole process
starts over.

The other NAND gate is a 48 decode (16 + 32) that goes low
from a count of 48 through 48 + 15 = 63, but of course the
count never reaches 63.

9. ### Lord GarthGuest

Now THAT I didn't notice. Does your data sheet top out at Q12?

10. ### Lord GarthGuest

The lovely picture is because we're in an non-binaries group. Did you
view with Courier?

That is strange that they didn't begin with Q0 as is the norm. can you

11. ### John PopelishGuest

John Popelish wrote:
....
I forgot the punch line:

So at a count of 60, both NAND gates go low for the first time.

12. ### GregGuest

I don't think I explained my question properly. I understand that both
of the NAND gates are outputting high normally and either gate will
only go low when both inputs are high. So once 32+16 goes high one of
the NAND gates will go low and when 4+8 goes high the other NAND
output will go low.

My specific question refers to feeding both of these outputs into the
OR gate. My understanding is that if either one input OR the other is
high the output of the OR gate will be high. So, the OR gate will
pulse when 4+8 goes high or 32+16 goes high. (On thinking about the
specific circuit now, though, when 4+8 goes high it will reset the
counter so that it will only count 12). I think I'm starting to
confuse myself, sorry if it sounds unclear.

Greg

13. ### Michael BlackGuest

I've seen them denoted both ways. An obvious example is Don Lancaster's
"CMOS Cookbook", where pin 9 is labelled "1". Indeed, I've used that book so
often that it's the one place I can immediately think of, so maybe it's the
exception rather than one of a number of places that use the form.

It can be confusing, because if you expect one, then it throws you off
when you come across the other.

Michael

14. ### GregGuest

Okay, I realise, now, the flaw in my logic. I had forgotten that the
OR gate is staying high until both NAND gates went low. I'd also
forgotten that the Schmitt trigger / inverter was taking the low pulse
from the OR gate and giving the one second pulse. Or, IOW, I got my
highs and lows confused.

Thanks for the patience. Now that I see how where I got confused, I
feel like an idjit.

Greg

15. ### Lord GarthGuest

That's a well written book. I've read all of Don's books in the early years
(thanks Don!)

As I recall NOW, the ripple counter simply omitted the first output in order
to make pins available. I fell for the "trap".

16. ### Rich GriseGuest

Okay, I realise, now, the flaw in my logic. I had forgotten that the
OR gate is staying high until both NAND gates went low. I'd also
forgotten that the Schmitt trigger / inverter was taking the low pulse
from the OR gate and giving the one second pulse. Or, IOW, I got my
highs and lows confused.

Thanks for the patience. Now that I see how where I got confused, I
feel like an idjit.[/QUOTE]

No need - this is s.e.basics.

Check out DeMorgan's Theorem:
http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/demorgan.html

Cheers!
Rich