Boost converter 12V to 36V (25 mA load) using 555

[abuhafss]

Coming to my current requirement, I checked and found I have UC3843 with me.
Can it be used? If yes, please suggest me a suitable design.
For your ready reference the datasheet is attached.

 

[KrisBlueNZ]

Yes, the UC3843 will work. There are lots of designs around.

http://www.google.com/search?q=UC3843+boost+converter&tbm=isch

I couldn't say which one is best. Avoid any designs that have the MOSFET's source grounded. It should go through a current sensing resistor.

The ON Semiconductor data sheet has more information than the Fairchild one you posted, but it doesn't have a boost converter design; only a flyback converter. They are similar though.

 

[abuhafss]

Kris

I have just copied your design on LTSpice (with traditional schematic model of 555, for my convenience). Labelled all the components and nodes as yours. The only different component is D1.

Here is the output with polarlized COUT.



He it is with a non-polar COUT.



Here are outputs for VC1 and I(L):



Would you please comment why the red & blue traces are different from yours. And why green trace is disturbed by a polarized COUT?

 

[KrisBlueNZ]

I don't know why there's so much noise when you use a polarised C_OUT. What ESR have you specified for the capacitor? Also you could temporarily try a 1N5819 for the output diode to see whether it makes any difference.

The red trace is just upside down. See it varies from about 0 µA to about -320 µA. You can either change the formula for that trace so it's "-I(L1)" instead of just "I(L1)", or you can reverse the inductor symbol in the schematic and graph it again. See that your L1 is rotated 180 degrees from the L1 in my schematic. This just means that when you click on the inductor in your schematic to graph the current through it, LTSpice graphs the current flowing from right to left, instead of the current flowing from left to right.

The blue trace looks the same as the timing capacitor voltage on my simulation, except that your simulation takes longer to enter regulation than mine - about 6.5 ms for yours, and 4.5 for mine. I don't know why they're different, but I don't think it's important. Here's the trace from my simulation for the first 7 ms. It looks a lot like yours.

 

[abuhafss]

I have tried all the polarized 10μF 50V (ESR = 1.0, 1.4, 2.4 and 2.5) available in my installation of LTSpice. All give the same result. Yes, I had changed the diode before reporting you but, no change

How silly of me, I ignored the direction of coil symbol.

 

[abuhafss]

The diode has to be a Schottky, I changed to ZHCS1000. The output has improved but still it is not as fine as yours.

 

[abuhafss]

Here you may see the difference in output trace with different types of C-OUT.

 

[KrisBlueNZ]

Why do you say the output diode "has to be" Schottky? What happens if it isn't?

Can you repeat the first and third graphs from post #47 but add the waveforms for:

• Voltage on the drain of the MOSFET (Q1), and
• Current through the inductor.

 

[(*steve*)]

There are several reasons for specifying a Schottky diode:

1. low capacitance
2. Fast switching
3. low forward voltage drop

All three contribute to lower power losses. Using a 1N4001 as a rectifier in one of these circuits would actually be really instructive for you or Kris to demonstrate.

However as Kris rightly questions, the statement that it must be a Schottky diode is not true. One of the issues with Schottky diodes is the poor reverse leakage performance and generally low reverse breakdown voltage. Especially in boost applications this can be a problem.

What you would typically use is a fast diode with a soft recovery. The soft recovery will reduce the amount of radiated EM noise.

Google "SMPS soft recovery diode" for more information. Here is a very useful video.

 

[abuhafss]

Without a Schottky + Polarized C-OUT, the output is shown in the first graph of post #43..
With s Schottky + Polarized C-OUT, the output is shown in post #46.

Here is the first graph from post #47 with V(drain) and I(L1).



And the third graph with V(darin) and I(L1).

 

[(*steve*)]

Unfortunately on my phone I don't see the post numbers, so its hard to see exactly what you mean.

What non-schottky diode did you choose? You can't just choose diodes at random. The diode must be suited to the task.

 

[abuhafss]

Unfortunately on my phone I don't see the post numbers, so its hard to see exactly what you mean.

What non-schottky diode did you choose? You can't just choose diodes at random. The diode must be suited to the task.

I have been using UF4007 as recommended by Kris but the output gets disturbed with it as shown in the first graph of post #43. And for your quick reference post #43 is right after the post in which Kris confirms:

"Yes, the UC3843 will work. There are lots of designs around."

 

[(*steve*)]

I don't see any real problem with the UF4007 in that post.

The issue with the capacitor is that the electrolytic is probably modeled with series resistance and inductance whereas the generic capacitor may be a pure model.

 

[(*steve*)]

Here you may see the difference in output trace with different types of C-OUT.

Oh, try an ESR of 0, then try 0.1 as a more realistic figure.

 

[abuhafss]

Oh, try an ESR of 0, then try 0.1 as a more realistic figure.

Yes, it gets improved at ESR = 0 and gets disturbed at 0.2

 

[abuhafss]

I don't see any real problem with the UF4007 in that post.

The issue with the capacitor is that the electrolytic is probably modeled with series resistance and inductance whereas the generic capacitor may be a pure model.

Kris' simulation didn't had that problem. So have to wait for him to reply which capacitor model did he used.

 

[(*steve*)]

Yes, it gets improved at ESR = 0 and gets disturbed at 0.2

Improved, or fixed at ESR = 0?

I think this is simply an indication of how important ESR is in this instance.

 

[abuhafss]

Improved, or fixed at ESR = 0?

I think this is simply an indication of how important ESR is in this instance.

Fixed

 

[(*steve*)]

Excellent.

This is probably the best introduction you could get to ESR and why it's so important to have low ESR capacitors in switchmode power supplies.

Switchmode power supplies work by placing high current pulses into a capacitor which the load then draws out of the capacitor.

In a perfect world, the current causes the capacitor voltage to ramp up, an d the load causes it to ramp back down.

However in real life ESR gets in the way. ESR is effectively a resistance in series with the capacitor. When the current pulse arrives, rather than the capacitor voltage rising slowly, it suddenly rises by a value given by IR, where I is the inductor current and R is the capacitor ESR.

As the current through the inductor falls to the load current, the current through the capacitor falls to zero and the voltage across the capacitor falls to the calculated capacitor voltage.

As the current through the inductor falls further, the capacitor voltage drops by IR (where I is the capacitor discharge current and R is the ESR. In additon to that, the voltage falls as the capacitor discharges.

So instead of getting a ramp up as the capacitor charges, and a ramp down as it discharges, we get a spike then a ramp down, then a spike, and a ramp down. This is exactly what you've seen.

 

[abuhafss]

Excellent.

This is probably the best introduction you could get to ESR and why it's so important to have low ESR capacitors in switchmode power supplies.

Switchmode power supplies work by placing high current pulses into a capacitor which the load then draws out of the capacitor.

In a perfect world, the current causes the capacitor voltage to ramp up, an d the load causes it to ramp back down.

However in real life ESR gets in the way. ESR is effectively a resistance in series with the capacitor. When the current pulse arrives, rather than the capacitor voltage rising slowly, it suddenly rises by a value given by IR, where I is the inductor current and R is the capacitor ESR.

As the current through the inductor falls to the load current, the current through the capacitor falls to zero and the voltage across the capacitor falls to the calculated capacitor voltage.

As the current through the inductor falls further, the capacitor voltage drops by IR (where I is the capacitor discharge current and R is the ESR. In additon to that, the voltage falls as the capacitor discharges.

So instead of getting a ramp up as the capacitor charges, and a ramp down as it discharges, we get a spike then a ramp down, then a spike, and a ramp down. This is exactly what you've seen.

Got it. Thanks