I've had a bit of a play with the 555-based design from post #18 in LTSpice.
I don't like the fact that there's no monitoring of the current in L1. This is likely to lead to saturation, and loss of the magic smoke from the MOSFET.
Also with the original design, the ON time of Q1 is too long for a 100 µH inductor at 12V; with C1 = 2n2 the ON time is around 16 µs, and the increase in inductor current can be calculated from:
dI = dT V / L
= 16×10
-6 × 12 / 100×10
-6
= 1.9A
That's far more peak current than you need; for a 25 mA load and a step-up ratio of 3, your peak inductor current should be about 300 mA.
For a 100 µH inductor, that corresponds to an ON time of 1.667 µs, which is pretty fast for a 555. So I tried increasing the inductor to 470 µH and recalculated the required MOSFET ON time.
dT = dI L / V
= 0.2 × 470×10
-6 / 12
= 7.8333 µs
Next I changed the operating mode of the 555. You really want it to operate more as a pulse generator, generating high output pulses with a fixed width of about 8 µs. So it should operate a bit like a gated oscillator: when the feedback voltage from the zeners drops low enough, it should produce an 8 µs high pulse to the MOSFET.
This can be done by changing the charge path for C1 so that instead of being charged directly from the 12V rail, it is charged only when the OUT pin is high. This is done using a diode and resistor from OUT to pins 2 and 6.
The fundamental problem is inductor saturation at startup. During the first 5~10 switching cycles, when the output voltage is only slightly higher than the input voltage, there is very little voltage difference across the inductor when the MOSFET is OFF, and the magnetic field, and the inductor current, only drop slowly. You can see this from the formula dT = dI L / V; as V approaches zero, dT approaches infinity. Since the inductor current doesn't fall much between pulses of energy from the MOSFET, the inductor current climbs quickly at startup, like a staircase, at the start of switching.
Inductor saturation at startup can be avoided by monitoring the actual inductor current, and simply locking out pulse generation while it's over a certain point. This is a general way to design a boost converter - turn the MOSFET OFF when the inductor current reaches a certain value; this is how current mode controllers work (the inductor current is sensed in the path between the MOSFET's source and the 0V rail, for convenience). Most of the boost converters I linked to in my earlier post use current mode control, which is a good technique because it detects and prevents inductor saturation problems directly at the source (pun intended).
I modified the circuit again by adding a 2.2Ω current shunt resistor (marked RS) in series with the inductor, and a PNP transistor, Q2, monitoring the voltage across that shunt resistor. As soon as the voltage reaches about 0.7V (which corresponds to an inductor current of about 320 mA), the transistor conducts and charges the timing capacitor very quickly. The timing capacitor in fact has almost no effect on the ON time of the MOSFET, and I removed the path from the 555's output through the diode to the timing capacitor with little effect on the circuit.
The timing capacitor and the resistor from it to 0V (which I've called RT) now determine the minimum OFF time, which determines the maximum voltage step-up ratio. That small change (adding Q2) has simplified the design quite a bit. It also prevents the 555 from starting up until the initial power-on current surge has finished; during that time, Q2 is saturated, the CT voltage is held near to VCC, and the 555 does nothing.
The RT value is not critical. With CT = 1 nF and L = 470 µH, RT = 3k3 gives continuous conduction until the regulation kicks in. With RT = 10k there is discontinuous conduction before regulation kicks in, so the startup time is a bit longer - about 6.5 ms. So I chose 5k6 as a compromise
So here's the schematic that I've ended up with:
I've changed Q1 to another smallish MOSFET with a lower ON-resistance. I've used a 1N5819 for D1 because my LTSpice installation doesn't have the UF400x series; you should continue to use a UF400x in your circuits.
And here are some graphs from the simulation:
This graph shows the first 5 ms of operation from power-up. The green trace shows the output voltage, using the legend at the left side. At point B, around 4.2 ms, the output voltage has reached around 36V and stabilises due to the zener regulation.
The red trace shows the inductor current, using the legend at the right side. At the start, at point A, you can see that the inductor current was very high. With the values I used, it starts off at about 2.7A. This is way above its saturation current but that doesn't matter; no switching is occurring, and no current is flowing in the MOSFET. This is just the initial current required to charge C
OUT.
The rest of the time, you can see that the inductor current always peaks at around 320 mA. This is the point where Q2 starts to conduct. This is shown in more detail later.
The blue trace is the voltage on CT. It is not very useful in this view.
This graph shows the very start of operation. Point A is marked again. Operation begins when the inductor current drops below about 300 mA and Q2 turns OFF, allowing the CT voltage (blue trace) to start to fall, as CT discharges through RT. Once this voltage reaches the 555's low threshold (1/3 of the VCC voltage), the 555 output goes high and the inductor current starts to ramp up again.
From that point onwards until regulation kicks in, the circuit operates as shown in the next graph.
The inductor current is shown in red, using the right hand legend. The voltage on CT is shown in blue, using the left hand legend.
Once CT voltage goes below 1/3 VCC (the 555's falling threshold voltage), the 555 drives its output high, turning on Q1. This causes the inductor current to increase. At point C, the inductor current is approaching the level where the voltage drop across RS is enough to bias Q2 into conduction; you can see the CT voltage starts to level off. Between points C and D, conduction in Q2 is increasing - first gradually, then rapidly, pulling the CT voltage upwards towards VCC. At point D, with the inductor current at 320 mA, Q2 is conducting quite heavily and the blue trace (CT voltage) is nearly vertical.
As soon as the CT voltage hits the upper threshold of the 555 (2/3 of VCC), the 555's output goes low, and Q1 turns OFF, and the inductor voltage (drain of Q1) "flies back" as energy from the inductor is dumped into the load. This is shown in the next graph. The inductor current ramps down again, and CT begins to discharge again through RT until the 555's lower threshold voltage is reached again, when the cycle repeats.
This graph shows the point where regulation kicks in, i.e. the output voltage is high enough that current through D2 and D3 prevents CT from discharging all the way to the 555's falling voltage threshold.
The graph does not show the CT voltage; it shows the inductor current in red (right hand legend) and the Q1 drain voltage (green, left legend).
You can see that when Q1 is OFF, and the inductor current is falling, Q1's drain voltage is about 36V. This is due to the back EMF from the inductor as it dumps its stored energy into the load. The flat top corresponds to a steady transfer of energy through D1 into C
OUT and the load.
Around 4.2 ms you can see the first discontinuous cycle; that is, the first cycle where the inductor current reaches zero because the MOSFET OFF time is now longer than the time taken for the inductor to dump all of its energy into the load. Subsequent cycles show the inductor "ringing" with the parasitic capacitance (in the inductor, Q1, and D1) as the last bit of energy decays to zero. The ringing is interrupted by the next MOSFET ON pulse, which pulls Q1's drain hard to 0V.
This design seems to simulate fairly well. I would be interested to know how it performs in real life. I suspect it will be noisy - both electrically, and audibly. I suspect it will suffer from "subharmonic oscillation", which is where a pattern emerges over a period of 2, 3, 4 or more cycles, that causes an audible sound from the inductor. This can be quite irritating and is often made worse if the load current varies significantly, since reduced load current causes the switching rate to drop from the maximum of 50 kHz during startup and overload, to something much lower.
In the simulation, reducing the load current to 10 mA (40% of specified) causes the switching frequency to drop to about 12 kHz! This is well within the audible range; even at higher frequencies, the subharmonic oscillations can be very audible.
If you build this circuit up, please let me know how it goes