Ban said:
The circuit you showed here has severe limitations.
1. It is unstable at open circuit, because the positive and negative
feedback dividers are equal for achieving high output impedance. Since you
didn't model the driver opamp on the pos. Input, you couldn't discover this.
2. Emitter followers are prone to oscillations at transit frequencies.
3. There is no current limitation when the opamp saturates.
4. output capacitance is bigger on the emitter.
5. The quiescent bias is undefined and temperature dependent.
6. The bootstrap is unsuitable for an application like this.
7. The output current can not cover the whole range with only one set of
resistors. Offset voltage drift etc. Your 3 offset resistors are ridiculous,
another +/-10K temperature change and everything has changed.
First of all you should think about what you want to measure.
Today it will be very useful to measure Vcesat, which requires to inject
base and collector current simultaneously at a fixed ratio. Ic needs to be
much higher (at least 10A) to be useful.
Hfe measurements should be done at different fixed Vce with defined Ic.
If you build a tracer, grounding the case and collector/drain will avoid
short circuits.
Unipolar current sources with switchable polarity will avoid damage on the
DUT. etc...
Ban,
Thanks, very much. Those are exactly the types of criticisms that I
was wanting to get.
Point taken, about the offset resistors! I had only stuck those in
there to get near zero offset for further simulations, until I could
get around to looking at temperature compensation, and also
offset-related issues, in depth. Any ideas about those (and anything
else, of course) would be most welcome. Perhaps I could just
substitute a thermistor-resistor network, there.
Because I am relatively inexperienced, I will have to do more research
on the rest of your comments. But please note that this circuit
(however it eventually is designed) will only operate with a
relatively-small number of pre-defined, switch-selectable operating
conditions: six sweep-voltage (e.g. DUT collector) p-p levels (1, 6,
12, 18, and 30V p-p, with selectable polarity of pos only, neg only, or
both), six frequencies (60, 200, 750, 12k, and 22k Hz, currently), and
12 base/gate-step-sizes (with staircase inputs to this circuit of from
0 to 15V or -15V, down to 0 to 200uV or -200uV, only one polarity at a
time; or, zero input).
[Regarding my modeling of the circuit: I did not think that I needed to
post more of it, for this discussion. But I DO have a functioning
Spice model for this entire subsystem, that includes all of the driving
stages, including the complete staircase generator and its attenuator,
buffers, selector switches, etc, and the complete sweep generator, also
with staircase's clock-pulse and oscilloscope blanking-pulse
generators, ramp generator's dielectric-absorption-compensation
feedback subsystem, and more. I also have complete, functioning Spice
models for all of the other subsystems of the Curve Tracer. And, in
many parts of the models, I also attempted to model effects such as PCB
trace inductances, parasitic capacitances of resistors, et al.
Everywhere, all capacitors' ESRs are modeled (from specs), too. In
LT-Spice, it can start out as an overall block diagram of the whole
Curve Tracer. And then I can burrow down into the blocks, all the way
to the schematic and component levels, although, of course, I normally
simulate just a single sub-system, or less, at one time.]
Note that a breadboarded version of the circuit being discussed (but
with some modifications that have been discussed), when temporarily
integrated into an existing version of the Curve Tracer's PCBs, seems
to function fairly well, when tested with various types of
transistors-under-test.
The only real "problem" variables that I can see that remain are
temperature and load. (Remember, though, that I am relatively
inexperienced.) But so far, at least, in the informal, random-device
testing that I've already done with it, this particular circuit seems
to do a fairly-GOOD job of maintaining constant and accurate step
currents, when a BJT-under-test has its base connected to the circuit's
output and is exercised with the available sweep signals (and similarly
for step voltages, with FETs).
I haven't yet found another type of circuit that can do it as well,
although, I HAVEN'T yet had time to test Jim Thompson's new circuit,
and am not yet familiar with very many of the possible alternative
circuits. But, since there are real objections to this (Howland)
topology, I am also still looking for a better way. (And, I haven't
yet really begun to look at temperature compensation for this circuit,
either.)
Just for completeness' sake, I should note that...: The
transistor-under-test will always have a one-ohm current-sense
resistor, to ground, on the terminal opposite from where the sweep
voltage is applied. And the sweep voltage is applied through a
switch-selectable series current-limiting resistor, ranging from 10
Ohms to 5 megOhms, limiting maximium sweep current to 1.5 amps. I
also neglected to mention, in earlier messages, that there are two
small cooling fans in the unit, one of which blows almost directly onto
this circuit.
Thanks again, Ban. More info always welcome.
Regards,
Tom Gootee
