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Bizzare behaviour from SG/UC3525

F

Fritz Schlunder

Jan 1, 1970
0
I have no experience of smps supplies, just posting
to register an interest in learning along with you.

Hand capacity effects around the Shutdown input?
A Shutdown input that is both directly connected to the
output OR gates, or is capable of doing an early PWM pulse
termination via the S-R flip flop?

Try sticking a 0.1uF from Shutdown to 0v, right at
the chip?


A 0.1uF capacitor on the shutdown pin is a step in the right direction, but
this pin should still not be left floating. It mentions this in TI's
UC3525A datasheet under the section: Principles of Operation and Typical
Characteristic Shutdown Options. Datasheet I'm looking at can be found:

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

So, a pull down resistor (or hardwiring to ground) should be used unless it
is actively being driven by something.
 
P

Pooh Bear

Jan 1, 1970
0
Fritz said:
It sounds like this is for your employment.
Yes.

Therefore my first
recommendation is that you might consider using an off the shelf powersupply

Not even remotely competitive with regard to price. Usually 2-3 X out of the
ball park. Been there looked at it many times with regard to smaller flyback
supplies. Also the 'form factor' needs to suit our product - not the other way
round ! We're also not making 100,000 + of these so they won't tool up a special
for us.
or working with a company that specializes in designing and manufacturing
SMPS designs specially for people such as yourself.

We did investigate a guy some yrs back who promoted himself in this respect. He
came up with a design that's astonishingly similar to that I mentioned elsewhere
in this thread that's made by one of the leading pro-audio amplifier
manufacturers ( actually their Mark One version of amp with smps supply ). I'm
not sure which one came first. His price was idiotic IMHO. I also know a company
that actually engaged him to do indeed what you suggest and he made plenty of
bangs himself and it took ages to tame !

You could spend all day
(weeks/months/perhaps even years) banging your head against the wall in
frustration. In the end you might end up with a product that seems reliable
and meets your requirements to your satisfaction only to find in your horror
that once deployed in the field it experiences all sorts of unanticipated
failures.

I'm normally the guy who then gets employed to fix it ! I have a track record of
resolving 'runaways' for other ppl. That's another story ( or several ).

Also - getting it right means we have the skill in house and can trot it out
thereafter every time we need it - which will be often - trust me. Once we have
the technology tamed we won't be using big line freq TXs anymore.
It is very easy to overlook things in an SMPS even when it seems
to be operating well. If you are a generalist doctor (or even a podiatrist)
you probably have no business performing heart transplants when there are
plenty of heart surgeons available.

But this is no ordinary heart. It's not a type of design that neatly falls into
most categories that an average psu designer would have met anyway !

Nevertheless for your own edutainment it would still be very valuable to
pursue the causes of your current SMPS ailments on your own time.

I've done the required development very successfully in my employment time with
regard to flyback designs.

Are you simply suggesting 'get someone else' who'll take another yr to make
something that half works ? I've seen companies do that. I've seen what 'blokes
who know' design. I'm not sure sometimes if I should laugh or cry. There is *no*
way we can afford to be so sloppy. Managers like this approach though since it
isolates them from responsibility - i.e. blame culture.

Anyway - that's not going to happen. I've never failed to take a project to a
succesful conclusion.

I'm not one who shrinks from acquiring new skills. I also design audio DSP now.
I didn't do that a couple of yrs back either. My effects ( reverb etc )
algorithms have been *very* well received ( i.e. bettter than what's typically
available from OEMs out there ). That's the point of learning to do it yourself
- You're in control and can make it *better* than the usual junk. It's what I
call R&D.

By the sounds of it your design has multiple weaknesses/problems which may
or may not be directly related to each other.

In particular the IR2110 seems to have attracted your intense scrutiny,
however I would venture to guess it is probably only an innocent victim.

Quite possibly so.
As
for the OutA/OutB jitter/unequal pulse width problems (as well as the human
hand near the design and it changes performance), this can probably be
explained by either your implementation of or your understanding of 3525
pins 1, 2, 8, 9, and 10 (for dual inline package).

1 and 2 are tied since we only need max duty cycle. 9 is therefore open - we
don't use the error amp at all. 8 has the usual cap to gnd.
These are all extremely
important pins which are normally driven by relatively high impedance
signals. They are quite sensitive and are quite integral to the control
loop and the general proper functioning of your device.

In particular the shutdown pin is not "slow acting" like you have theorized.
It would appear from the block diagram that even a very momentary high
signal on this pin will instantly turn off the output NOR gates, as well as
set the PWM latch thus keeping the outputs off until at the very least the
next cycle of the oscillator. How fast the outputs turn back on depends on
what happened to the soft start capacitor.

As far as I saw, the shutdown pin simply discharges the soft start cap. I *know*
it does this slowly since asserting shutdown briefly *doesn't* immediately reset
the duty cycle to zero. This is a failure in someone else's implementation of
this part that I'm aware of. I put a 555 mono there to stop that. It gets a damn
good long shutdown signal from me.

As for your IR2110 fizzling... It seems to me that if the output IGBTs
haven't failed,

They do normally !
then clearly something is very wrong. I guess that is
obvious since the IR2110 failed...

Yeah - that really puzzled me. Only happened that way once after I put a 10nF
decoupling cap to gnd local to the shutdown pin. I haven't tested the theory
that the 2 are related since I'd run out of a supply of spare IR2110s at the
time !
Without a schematic it is very hard to
say exactly what you are doing and how turning off the 3525 might have
effected the IR2110. What is the nature of your powersupply source for the
3525 and IR2110? Maybe one theory might be the IC bias powersupply is not
properly regulated, and when the 3525 load was removed the voltage overshot
way exceeding the IR2110 absolute maximum rating.

No. It's just a classic line freq TX with cap filter. It'll be a baby flyback
switcher in production / next incarnation. Used a line freq tx for now simply
for convenience. 1000uF of filter cap btw. Vsupervisory is about 14V typ. I'll
make it a couple of volts higher on the real thing. No significant ripple
voltage on it either.

Another theory that I
had, but consider quite unlikely, is that perhaps when the 3525 turned off
the output effectively went high impedance, and perhaps stray capacitance
was coupling the output of the IR2110 signal back to the inputs, thus
causing it to oscillate at high frequency.

That theory would indeed tend to explain such 'odd' behaviour. I'd believe that,
if it wasn't that this certain company is making tens of thousand of these units
every year with proven reliability that are the industry norm that couples these
exact same 2 devices exactly the same way as me too !
In this case, perhaps the IR2110
internal power dissipation grew too large and it subsequently toasted. I
find this theory unlikely however since the IR2110 inputs have schmitt
triggers and internal pull down resistors, and the input/output phasing
would have to be inverted for this to happen.

Whatever the cause of this problem, it sounds like it has a relatively low
chance of being directly related to your other pulse width/jitter problems.
I would not look directly at the IR2110 for the source of your problem as
much the circuitry surrounding and hooked up to the IR2110 for the root
cause.

I think you're right.
Aside from these considerations... Current limiting? You are using it
right? Right??

Implemented my own way using a current sense R in the return path to the Vbus
centre tap.

I've got an LM393 looking at + - volts across the current sense shunt and
sending a level shifted signal to a 555 mono that then asserts shutdown on the
3525. I used a 555 since I saw in advance that shutdown on the 3525 wasn't fast
acting.

Been tested ( adjusted the sensitivity to play with it ) - works a treat. It
does that perfect 'burp mode'.

Without it you are liable to get some kind of STD

STD ? I rather think you don't mean sexually transmitted disease ! That acronym
I'm not familiar with I regret.
or
something. Any high power SMPS which has any hope of being remotely
reliable must implement some kind of highly effectual current limiting.

Perfectly understood.
The
soft start and shutdown pins of the 3525 may play some role in a given
current limiting implementation, but it is up to you to decide exactly how
best to do it in your application.

I agree.
I personally like implementations that
have two levels of safety. One level instantly shuts off the output as fast
as possible (IE: <1us, preferably <<1us) upon detection of excessive
instantaneous current, but doesn't latch the output off for very long (IE:
perhaps only for the remainder of the given PWM cycle).

Cycle skipping in effect ?
The other level of
safety measures the time averaged current and shuts the device down for
several cycles upon detection of excessive average current. The fast cycle
by cycle current limit is the best, but unless it is extremely fast

Yes !
it may
not be able to keep the average duty cycle sufficiently small under all
conditions, depending upon how it was implemented.

Which why I didn't follow brand X's method.
Keep in mind that any
current limiting scheme has the potential to interfere with the voltage
control loop whenever it gets activated.

There is *no* voltage control loop. The psu is run open-loop. Vout = Vbus / tx
ratio. In fact in this instance being a half-bridge there's 160V typically
across the tx primary and the centre tapped secondaries on the main outputs are
also 80-0-80.

See my previous introductory comments about why this is done for huge audio
amplifiers. Actually this is the tiddler ! The bigger one will provide around +
- 130V @ 50 A pk ! Times 2 chs. And idle current is about 50mA !

Thanks for your detailed and considered input.

Regds Graham
 
F

Frithiof Andreas Jensen

Jan 1, 1970
0
Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Layout is critical ... and decoupling ... I have had trouble squezing enough
decoupling onto those chips before. Seem to remember that there is an
applciation note for the layout of that chip and that is pretty much *it* -
it will *not* work in any other way.
Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !

You are picking up noise, and the 3525 output drivers are perfectly fast
enough to generate it themselves. The driver chip probably plenty fast also.
Maybe you slam the supply rails together.

Once you get the good scope out, you will see that one of the pins of the
3525 *will* have a tiny 6 ns spike on it, which will reset the latch in the
chip. causing more spikes to be generated.
 
P

Pooh Bear

Jan 1, 1970
0
Tony said:
I'd be tempted to link the Shutdown pin to 0V and
do external shutdown with a clamp across the slow
start capacitor. This would avoid uncontrolled
re-starts if the shutdown command glitched.

You just read my mind !

One 'jellybean' transistor should do nicely.

Perhaps use a MOSFET with pullup to 12V so that
any global undervoltage circuit has to generate
an active pulldown to keep the 3524 Enabled.

This is where it gets fun - trying to second guess how the part actually
works !

;-)
The SG3525 data sheet does not say what happens to
the (active) logic-low levels of the OUTs when it's
power supply goes below 8v.

I bet it doesn't !

You read my mind - *again* ! I've been 'sleeping on it' btw.

At some unknown low
supply voltage the OUTs might go to an open circuit.
Would it be prudent to have safety pull-down R's on
the IR2110 inputs?

I suspect we're heading towards a solution here.

Thanks, Graham
 
P

Pooh Bear

Jan 1, 1970
0
Fritz said:
This is a good point, however it appears the designer of the IR2110
envisioned this scenario and took care of it. Presumably the IR2110 inputs
have both schmitt triggers and internal pull downs.

They did it seems !

That's interesting. Makes a pleasant change !

Graham
 
F

Fritz Schlunder

Jan 1, 1970
0
It seemed to stop the 'jitter' on the trailing high side edge but then I
went and switched the damn thing off and the IR2110 went Fizzzz as the
rails decayed ! And it was the the *low* side driver that had gone bad !
It measured 2 ohms form Vs to out after this incident !


It usually takes quite a bit of power to make a component audibly fizzle.
While not totally inconceivable, a 14V bias supply (which was just turned
off before the failure, is that what you are suggesting?) isn't too likely
to be able to deliver this much juice. So that leaves the question, if it
didn't come from the IR2110 supply rail, where did the power come from?

Perhaps the power came from the main input capacitor(s) charged to what,
340V? The IR2110 is connected to this high voltage supply, so this isn't
totally inconceivable even if the IGBT gates don't get blasted.

After the failure, did you check to see if the bootstrap diode (which is
used by the IR2110 to charge the bootstrap capacitor Cboot) was still good?
What is the part number you are using for this bootstrap diode? If this
part failed it could conceivably cause the symptoms described. The
temptation when selecting this part would be to use a low voltage schottky
diode, however this would not be a good choice since the part must be able
to block the full high voltage supply voltage plus around 15V plus margin.
During turn off of the IR2110 Vcc supply it is conceivable this diode would
experience slightly higher voltage stress than during normal operation. If
improperly selected, this might help explain why it failed at power off.
This may not be your problem, but it is a theory at least.


What does your power stage look like? Do your half bridge IGBTs have
antiparallel diodes on them?

This is probably unrelated, but 14V is rather too low by conventional
standards for driving normal IGBTs. Normal IGBTs expect about 15V of gate
drive for good performance, and since the high side IGBT will only receive
at the most one diode drop less than the IR2110 bias supply voltage, this is
a bit lower than what is conventionally considered optimum.
 
R

Rich Grise

Jan 1, 1970
0
The 3525 is simply being used to generate the timing waveforms. The 3525
outputs drive an IR2110 half bridge arrangement.


It's a configuration very similar to one used by one of the major
pro-audio amplifier companies in a mildly different incarnation which
has proven reliability. The differences are modest and I've added some
further protective features in fact.


Not that I can post right now sadly.

Well, I should know better than to look at data sheets in my delicate
condition *hic*, but you _did_ say that the low side went pfft? Where
does it get its Vcc? Plus, I don't trust black boxes in general. ;-)

Thanks,
Rich
 
F

Fritz Schlunder

Jan 1, 1970
0
1 and 2 are tied since we only need max duty cycle. 9 is therefore open - we
don't use the error amp at all. 8 has the usual cap to gnd.


The datasheet doesn't seem tremendously clear, but pin 9 (compensation)
doesn't appear to have a tremendously strong driver. Although I doubt this
is causing any problems, it may be at least conceivable very powerful noise
could disrupt this signal. They show a 10nF capacitor hooked up to this pin
in their lab test fixture.

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

I doubt this is your problem, but you might try putting such a capacitor in
place just to verify this to be the case.

The more you write about it, the more suspect in my mind pin 10 becomes
however (shutdown).

What exactly do you have all hooked up to the shutdown pin and how?
As far as I saw, the shutdown pin simply discharges the soft start cap. I *know*
it does this slowly since asserting shutdown briefly *doesn't* immediately reset
the duty cycle to zero. This is a failure in someone else's implementation of
this part that I'm aware of. I put a 555 mono there to stop that. It gets a damn
good long shutdown signal from me.


Better go back to that datasheet I linked to above and re-read the text that
appears on page 6 again. When driven high the shutdown pin will instantly
turn off the output as well as set a latch that will keep the output off for
the remainder of the given oscillator cycle. This means the output won't
remain off for very long (as the output will turn back on again the very
next oscillator cycle) unless the shutdown pin stays high.

The shutdown pin does more than just this however. It also activates a
roughly 150uA current sink (extremely crude one if you study the block
diagram) which begins discharging the soft start capacitor. If the shutdown
pin doesn't stay high for very long, then the soft start capacitor voltage
will not appreciably change. In this case the pulses would resume normally
at full width the very next cycle of the main oscillator. On the other
hand, if the shutdown pin is asserted for long enough to significantly
discharge the soft start capacitor (through the roughly 150uA constant
current sink), then the device should exhibit soft start effects when the
shutdown signal is finally removed (actively driven to ground, the shutdown
pin should never be left floating).

They do normally !


That isn't encouraging news. What does your output power stage look like?
In particular what is the arrangement of the secondary(s) of the main power
transformer? How is the output rectified? Do you use two inductors on the
output for smoothing, or does the output of the transformer directly try to
charge the output capacitors through the rectifiers? What is the output
capacitance? Input capacitance and input voltage?


Implemented my own way using a current sense R in the return path to the Vbus
centre tap.

I've got an LM393 looking at + - volts across the current sense shunt and
sending a level shifted signal to a 555 mono that then asserts shutdown on the
3525. I used a 555 since I saw in advance that shutdown on the 3525 wasn't fast
acting.

Been tested ( adjusted the sensitivity to play with it ) - works a treat. It
does that perfect 'burp mode'.


If the output power stage doesn't use inductors (and maybe even if it does,
especially if the soft start feature doesn't function adequately), then the
restart will be extremely stressful, especially if the output capacitors are
large (which I assume they are). This can very easily lead to the
desruction of IGBTs with no clear cause or reason for failure. Presumably
the output capacitors store many joules of energy. If a capacitor is
charged from a voltage source (without inductance, or with a small amount of
inductance but in an uncontrolled fashion) the energy lost in the parasitic
resistance is equal to the energy stored in the capacitors after they are
fully charged. If the capacitors are allowed to charge rapidly and in an
uncontrolled fashion without inductance, the IGBTs represent the bulk of the
parasitic resistance and can therefore easily be destroyed. If the device
is operated in burp/hiccup mode then the uncontrolled rapid
charging/discharging/recharging stresses is all the worse. Device failure
(presumably thermal failure) can occur even when the package is physically
cool to the touch.

STD ? I rather think you don't mean sexually transmitted disease ! That acronym
I'm not familiar with I regret.

It seems you know the acronym I was referring to.
 
F

Fritz Schlunder

Jan 1, 1970
0
After others' comments I'm going to concentate on pin 10 - the shutdown pin.
Despite the fact that the block diagram of the chip's internals shows no
obvious route for this to cause the effect,


I'm starting to see where some of this confusion might be coming from. The
datasheets aren't very good.

On Texas Instruments datasheet:

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

They show the block diagram on page one. In that block diagram they show
how the internal connection is made between the shutdown input and the PWM
latch as well as directly to the NOR output gates. When a high input
voltage is provided at the shutdown pin (IE: 5.1V of Vref) current flows in
through the internal resistor activating the internal "1.4V reference"
composed of two diode drops as well as the crude current sink made by the
NPN and 5k resistor. Evidently this 1.4V is enough to be registered as
logical highs by the PWM latch and NOR gates.

I notice now that on the figure on page seven labeled "Lab test fixture"
they don't depict the internal connection between shutdown and the PWM latch
or NOR gates. I can see how that might make it hard to see why it should
instantly (typically 200ns, max. 500ns) deactivate the output.

ST's datasheet shows a similar picture. The block diagram shows the
connection while the lab test fixture does not.

http://www.st.com/stonline/products/literature/ds/4286/sg3525.pdf

Shame on ST and TI and whoever else does this in their 3525 datasheet. TI's
text fixture is a little better than ST's datasheet in that they didn't
leave pin 10 floating under any conditions.
 
T

Tony Williams

Jan 1, 1970
0
Pooh Bear said:
1 and 2 are tied since we only need max duty cycle.

From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1.
9 is therefore open - we don't use the error amp at all.

An open-collector comparator into pin 9 (COMP input)
is SG's first choice for pulse_by_pulse limiting.

They say that the Shutdown input can be used for p_by_p
but only when there is no capacitor on the Slow-Start pin.

Radical rethink needed Graham.......

Shutdown pin to 0v.
Your p_by_p Overcurrent comparator into COMP input.
Any external UVLO discharges the Slow-Start cap.
8 has the usual cap to gnd.

What value is it, and could you please measure
at some time what voltage it finally rises to?
 
T

Tony Williams

Jan 1, 1970
0
From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1. /|\
|
Misread. Should be N.Inv IN________|

The max CMV of the error amp is 5.2V, so it could
be possible to connect pin 2 to the 5.1V ref and
pin 2 at least 0.7V below it. This should put
the output of the error amp at 3.8Vdc.
 
T

Tony Williams

Jan 1, 1970
0
Fritz Schlunder said:
I'm starting to see where some of this confusion might be coming
from. The datasheets aren't very good.

I'm beginning to wonder whether a more modern chip
(LT1105?) might be easier/cheaper..............
 
P

Pooh Bear

Jan 1, 1970
0
Tony said:
From the SG3525 circuit of the error amp section
that doesn't make sense? Pin2 (-ve IN) should be
higher than pin 1.

Sorry. I didn't mean tied together !

One's tied low ( gnd ) and the other is tied to Vref.
An open-collector comparator into pin 9 (COMP input)
is SG's first choice for pulse_by_pulse limiting.

That could be potentially useful actually ! It's simply a no-connect on
my pcb at present.

And where did you get that nugget of info about the pulse limiting ?
That's very, very interesting.

They say that the Shutdown input can be used for p_by_p
but only when there is no capacitor on the Slow-Start pin.

Quite !
Radical rethink needed Graham.......

Interesting. That explains how Big Company A's implementation has a
failure mode I accidentally visited once. ;-)

Shutdown pin to 0v.
Your p_by_p Overcurrent comparator into COMP input.
Any external UVLO discharges the Slow-Start cap.


What value is it, and could you please measure
at some time what voltage it finally rises to?

It's 47uF currently since I deliberately wanted a very slow soft start
to look at it closely. It would be 4.7 or 10 uF in practice most likely.

And yes - I'll measure the volts there.

Cheers, Graham
 
P

Pooh Bear

Jan 1, 1970
0
Frithiof said:
Layout is critical ... and decoupling ... I have had trouble squezing enough
decoupling onto those chips before.

How much ( value, type ) would you typically use ? 0.1uF box film polyester type
here. An MLC type presents no probs to me but modern film types are pretty hot.

Seem to remember that there is an
applciation note for the layout of that chip and that is pretty much *it* -
it will *not* work in any other way.


You are picking up noise, and the 3525 output drivers are perfectly fast
enough to generate it themselves. The driver chip probably plenty fast also.
Maybe you slam the supply rails together.

Once you get the good scope out, you will see that one of the pins of the
3525 *will* have a tiny 6 ns spike on it, which will reset the latch in the
chip. causing more spikes to be generated.

That sounds suspiciously likely !

Graham
 
P

Pooh Bear

Jan 1, 1970
0
Fritz said:
Better go back to that datasheet I linked to above and re-read the text that
appears on page 6 again. When driven high the shutdown pin will instantly
turn off the output as well as set a latch that will keep the output off for
the remainder of the given oscillator cycle. This means the output won't
remain off for very long (as the output will turn back on again the very
next oscillator cycle) unless the shutdown pin stays high.

Yes, I follow you.

I rather suspect a draughting error on the data sheet !

As you say, it's not especially clear.

The shutdown pin does more than just this however. It also activates a
roughly 150uA current sink (extremely crude one if you study the block
diagram) which begins discharging the soft start capacitor. If the shutdown
pin doesn't stay high for very long, then the soft start capacitor voltage
will not appreciably change.
Yes.

In this case the pulses would resume normally
at full width the very next cycle of the main oscillator.

Yes. I've seen this.
On the other
hand, if the shutdown pin is asserted for long enough to significantly
discharge the soft start capacitor (through the roughly 150uA constant
current sink), then the device should exhibit soft start effects when the
shutdown signal is finally removed
Indeed.

(actively driven to ground, the shutdown
pin should never be left floating).

Now look at the application circuit ! Tell me if pin 10 isn't effectively
'floating' !

This data sheet is just truly awful.

That isn't encouraging news. What does your output power stage look like?

Just a plain vanilla half-bridge !

In particular what is the arrangement of the secondary(s) of the main power
transformer? How is the output rectified? Do you use two inductors on the
output for smoothing, or does the output of the transformer directly try to
charge the output capacitors through the rectifiers? What is the output
capacitance? Input capacitance and input voltage?

Haven't even got as far as rectifying anything yet, I'm just trying to get the
driver power waveforms right.

If the output power stage doesn't use inductors (and maybe even if it does,
especially if the soft start feature doesn't function adequately), then the
restart will be extremely stressful, especially if the output capacitors are
large (which I assume they are).

There are small Ls on the secondary side. I plan to look very carefully at the
current waveforms. I'm not going to be caught out by that particular one.
This can very easily lead to the
desruction of IGBTs with no clear cause or reason for failure. Presumably
the output capacitors store many joules of energy. If a capacitor is
charged from a voltage source (without inductance, or with a small amount of
inductance but in an uncontrolled fashion) the energy lost in the parasitic
resistance is equal to the energy stored in the capacitors after they are
fully charged. If the capacitors are allowed to charge rapidly and in an
uncontrolled fashion without inductance, the IGBTs represent the bulk of the
parasitic resistance and can therefore easily be destroyed. If the device
is operated in burp/hiccup mode then the uncontrolled rapid
charging/discharging/recharging stresses is all the worse. Device failure
(presumably thermal failure) can occur even when the package is physically
cool to the touch.


It seems you know the acronym I was referring to.

Lol !

Graham
 
P

Pooh Bear

Jan 1, 1970
0
Rich said:
Well, I should know better than to look at data sheets in my delicate
condition *hic*, but you _did_ say that the low side went pfft? Where
does it get its Vcc? Plus, I don't trust black boxes in general. ;-)

Yes, the last failure was indeed the low side driver. ( rolls eyes in
puzzlement ) Its Vcc comes from the same supervisory supply as everything
else. Locally decoupled. Didn't take any IGBTs out that time though. Just
literally fizzzzed as I removed power and the rails sagged. The 3525 shouldn't
have been switching at the time - I'd already asserted shutdown via a switch.

Graham
 
P

Pooh Bear

Jan 1, 1970
0
Fritz said:
It usually takes quite a bit of power to make a component audibly fizzle.
While not totally inconceivable, a 14V bias supply (which was just turned
off before the failure, is that what you are suggesting?)

Yes. It would have decayed slowly too but faster than Vbus.
isn't too likely
to be able to deliver this much juice. So that leaves the question, if it
didn't come from the IR2110 supply rail, where did the power come from?

Perhaps the power came from the main input capacitor(s) charged to what,
340V?

Yeah - 320V.
The IR2110 is connected to this high voltage supply, so this isn't
totally inconceivable even if the IGBT gates don't get blasted.

After the failure, did you check to see if the bootstrap diode (which is
used by the IR2110 to charge the bootstrap capacitor Cboot) was still good?

Actually I didn't. Interesting point but it worked when I replaced the IR2110 so
I guess it's fine. A UF4006. Fast 1A 600V.

What is the part number you are using for this bootstrap diode?

See above. ;-)
If this
part failed it could conceivably cause the symptoms described. The
temptation when selecting this part would be to use a low voltage schottky
diode, however this would not be a good choice since the part must be able
to block the full high voltage supply voltage plus around 15V plus margin.
Quite.


During turn off of the IR2110 Vcc supply it is conceivable this diode would
experience slightly higher voltage stress than during normal operation. If
improperly selected, this might help explain why it failed at power off.
This may not be your problem, but it is a theory at least.

I'll check it's a 4006 and not a 4004. Even so, the 4004 ( 400V ) should be
fine.

What does your power stage look like? Do your half bridge IGBTs have
antiparallel diodes on them?

The ones I'm currently using don't have the 'body diodes' so I have some MUR460s
in parallel. Fast 600V 4A.

This is probably unrelated, but 14V is rather too low by conventional
standards for driving normal IGBTs. Normal IGBTs expect about 15V of gate
drive for good performance, and since the high side IGBT will only receive
at the most one diode drop less than the IR2110 bias supply voltage, this is
a bit lower than what is conventionally considered optimum.

Yes, I agree. I just 'bumped up' the volts slightly actually. I plan to use a
regulated supply ( flyback switcher ) to supply this rail in the final version.
Probably about 16 ~ 17 V.

Graham
 
P

Pooh Bear

Jan 1, 1970
0
Fritz said:
I'm starting to see where some of this confusion might be coming from. The
datasheets aren't very good.

Tell me about it !
On Texas Instruments datasheet:

http://focus.ti.com/lit/ds/symlink/uc3525a.pdf

I notice now that on the figure on page seven labeled "Lab test fixture"
they don't depict the internal connection between shutdown and the PWM latch
or NOR gates. I can see how that might make it hard to see why it should
instantly (typically 200ns, max. 500ns) deactivate the output.

Good isn't it ! ;-)

ST's datasheet shows a similar picture. The block diagram shows the
connection while the lab test fixture does not.

http://www.st.com/stonline/products/literature/ds/4286/sg3525.pdf

Shame on ST and TI and whoever else does this in their 3525 datasheet. TI's
text fixture is a little better than ST's datasheet in that they didn't
leave pin 10 floating under any conditions.

Oh yes. You're right ! I'd previously taken the 2 data sheets to be effectively
clones. That's an intruiging difference. Could explain a few things !


Many thanks, Graham
 
T

Tony Williams

Jan 1, 1970
0
That could be potentially useful actually ! It's simply a
no-connect on my pcb at present.
And where did you get that nugget of info about the pulse
limiting ? That's very, very interesting.

Off a 1989 Silicon General data sheet, 6th page,
labelled Shutdown Options. Just above the test
fixture circuit.... which also leaves pin 10 open
when running.

Just to be sure. Pull COMP to 0v to do a shutdown
via the PWM stage and R-S flipflop.
It's 47uF currently since I deliberately wanted a very slow soft
start to look at it closely. It would be 4.7 or 10 uF in practice
most likely.

Resistor needed in series with the pulldown Tr then.
And yes - I'll measure the volts there.

Thanks. Best guess atm would be up near the 5v1 Vref.

BTW: It's only a 60uA pulldown current. If I assume
47uF, and a required pulldown from 4V to 0.5V,
then that would mean that the Shutdown pin has to
be held high for 2.7 seconds before a full (safe)
soft re-start can happen.
 
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