Bizzare behaviour from SG/UC3525

[Pooh Bear]

Hi,

you may have noted my posts about problems recently with my attempts to
make a high power smps.

I'll give a quick overview.

The application is a high power pro-audio amplifier.

Traditional psus use nice toroids that we know well. You can optimise
them for low copper losses that helps keeps weight down.

We want to make our amps lighter though. Like some competitors that are
also using SMPSs.

Various mfrs have used switch-mode techonology. The fixed duty cycle
approach appears to be universal. I expect this is since a classic
forward converter doesn't have the bandwidth to respond to audio
transients. Not to mention cross-regulation to other rails issues.

Unlike most 'forward converters' - see argument about this terminology
another day - PLS ! they run at a fixed duty cycle. I.e. max. Kinda 90%.

Ok - so that's the rough overview.

So - I have this pcb with my design that's 'plain vanilla' - no frills.
The 'control circuitry' i.e. SG 3525 and some other shit is located on a
plug-in pcb via a right-angle pcb header.

I work-up the prototype - the waveforms look right etc etc....

Then I get trouble as I've mentioned here before. The UVLO I can deal
with. If the parts can't 'agree' when to stop working I'll tell them
myself !

So - that one's fixed. Ok - finito. ( or so you might think )

Next problem - apparent 'jitter' on the trailing edge wavefom at the
load ( high side ) with high input volts on the highside drive. I
investigate this. I add a zener clamp on the highside IGBT for example
in case of gate resonance. No good. I modify the signal path to reduce
inductance. No good.

I then find by accident that if I try to 'provoke' the highside jitter
it's affected by my hand capacitance on the switch that I have included
to 'stop switching' to the shutdown pin on the 3525. Uh ?

I check the supervisory supply. I discover that if the supervisory
supply ( provides drive to the 3525 ) is higher than before - changed
transforner ratio - then the jitter occurs earlier ( I'm ramping the
input volts on a variac ).

I'm getting desperate.

So - I look at the 3525 output. OutA and OutB. I checked them earlier
and they look nice and clean.

I have a high resistance nominal load on the half-bridge output that
takes mere milliamps.

I see the switching waveforms. They look sensible at the load. Apart
from this funny 'jitter' on the high side that only occurs at high DC
bus volts when driving my TX ( no sec load ).

I feel I'm going mad.

Finally I get the sense to check the inputs to my IR2110 high side
driver ( from the 3525 ). Recall I checked these before populating the
pcb.

I see mismatched timing periods !

I have OUTA used as the high side drive signal . It looked fine before
but it's only 500ns long I discover ! OUTB is 4.5us long ( as it should
be ) !

I remove the IR2110 gate driver. The waveforms are perfect. Excellent
match between OutA and OutB.

I replace the IR2110. Mismatch occurs again. I've'blown' enough IR2110s
to not think they're the problem. How can the logic input loading of the
IR2110 affect a totem-pole output from the 3525 ?

So - is the 3525 at fault ? I'm careful only to change one item at a
time normally. I reckon maybe I should replace the TI 3525 with an STM
part ( actually that's 2 items at a time technically - but I didn't
expect my other TI sample to be any different ).

I do so. Goddamit if the same bonkers behaviour isn't replicated by
another part from a different vendor !

I check that my pcb man has allocated every pin correctly ( he has ) . I
read the data sheets looking for some mention of erroneous behavour. I
find nothing.

I noted in passing that the 3525 seemed to be sensitive to noise on the
shutdown pin. Odd, since the IC block diagram shows that to be a 'slow'
input. It has to discharge the soft-start cap. Soft-start is working
fine. But my grounds should be clean - I've got a Kelvin connection to
the low-side IGBT emitter mere cm away.

Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !


Graham

 

[Terry Given]

Hi,

you may have noted my posts about problems recently with my attempts to
make a high power smps.

I'll give a quick overview.

The application is a high power pro-audio amplifier.

Traditional psus use nice toroids that we know well. You can optimise
them for low copper losses that helps keeps weight down.

We want to make our amps lighter though. Like some competitors that are
also using SMPSs.

Various mfrs have used switch-mode techonology. The fixed duty cycle
approach appears to be universal. I expect this is since a classic
forward converter doesn't have the bandwidth to respond to audio
transients. Not to mention cross-regulation to other rails issues.

Unlike most 'forward converters' - see argument about this terminology
another day - PLS ! they run at a fixed duty cycle. I.e. max. Kinda 90%.

Ok - so that's the rough overview.

So - I have this pcb with my design that's 'plain vanilla' - no frills.
The 'control circuitry' i.e. SG 3525 and some other shit is located on a
plug-in pcb via a right-angle pcb header.

I work-up the prototype - the waveforms look right etc etc....

Then I get trouble as I've mentioned here before. The UVLO I can deal
with. If the parts can't 'agree' when to stop working I'll tell them
myself !

So - that one's fixed. Ok - finito. ( or so you might think )

Next problem - apparent 'jitter' on the trailing edge wavefom at the
load ( high side ) with high input volts on the highside drive. I
investigate this. I add a zener clamp on the highside IGBT for example
in case of gate resonance. No good. I modify the signal path to reduce
inductance. No good.

I then find by accident that if I try to 'provoke' the highside jitter
it's affected by my hand capacitance on the switch that I have included
to 'stop switching' to the shutdown pin on the 3525. Uh ?

I check the supervisory supply. I discover that if the supervisory
supply ( provides drive to the 3525 ) is higher than before - changed
transforner ratio - then the jitter occurs earlier ( I'm ramping the
input volts on a variac ).

I'm getting desperate.

So - I look at the 3525 output. OutA and OutB. I checked them earlier
and they look nice and clean.

I have a high resistance nominal load on the half-bridge output that
takes mere milliamps.

I see the switching waveforms. They look sensible at the load. Apart
from this funny 'jitter' on the high side that only occurs at high DC
bus volts when driving my TX ( no sec load ).

I feel I'm going mad.

Finally I get the sense to check the inputs to my IR2110 high side
driver ( from the 3525 ). Recall I checked these before populating the
pcb.

I see mismatched timing periods !

I have OUTA used as the high side drive signal . It looked fine before
but it's only 500ns long I discover ! OUTB is 4.5us long ( as it should
be ) !

I remove the IR2110 gate driver. The waveforms are perfect. Excellent
match between OutA and OutB.

I replace the IR2110. Mismatch occurs again. I've'blown' enough IR2110s
to not think they're the problem. How can the logic input loading of the
IR2110 affect a totem-pole output from the 3525 ?

So - is the 3525 at fault ? I'm careful only to change one item at a
time normally. I reckon maybe I should replace the TI 3525 with an STM
part ( actually that's 2 items at a time technically - but I didn't
expect my other TI sample to be any different ).

I do so. Goddamit if the same bonkers behaviour isn't replicated by
another part from a different vendor !

I check that my pcb man has allocated every pin correctly ( he has ) . I
read the data sheets looking for some mention of erroneous behavour. I
find nothing.

I noted in passing that the 3525 seemed to be sensitive to noise on the
shutdown pin. Odd, since the IC block diagram shows that to be a 'slow'
input. It has to discharge the soft-start cap. Soft-start is working
fine. But my grounds should be clean - I've got a Kelvin connection to
the low-side IGBT emitter mere cm away.

Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !


Graham

Gidday Graham,

try this: lift OUTA and OUTB pins. "swap" them with little dangly wires.

If the OUTA pin suddenly starts working and OUTB goes funny, then its
something to do with the external connection(s) to OUTA

then pull the same trick with the IR2110 inputs.

some gatedrive outputs get pissy when output inductance pulls them below
0V (or above Vcc). a SOT23 dual schottky on each output can eliminate
that potential problem.

try loading them capacitively (perhaps 10-20pF) sans IR2110, see if the
waveforms are still OK.

set the DC bus to 0V, provide a separate high-side power supply and see
what happens - with no actual output switching, does the problem occur.

place a series resistor between the 3525 & 2110, perhaps 1k.

Cheers
Terry

 

[Pooh Bear]

Gidday Graham,

Good day to you too Terry.

try this: lift OUTA and OUTB pins. "swap" them with little dangly wires.

Ummm... guess what I was thinking of doing next ! It's called desperation !

If the OUTA pin suddenly starts working and OUTB goes funny, then its
something to do with the external connection(s) to OUTA

Yuh . That figures. But a 1~2 cm track - with careful attention to routeing ?

then pull the same trick with the IR2110 inputs.
OK.

some gatedrive outputs get pissy when output inductance pulls them below
0V (or above Vcc). a SOT23 dual schottky on each output can eliminate
that potential problem.

Interesting.

I omitted to mention - for sake of simplicity- that I briefly decoupled the
3525 shutdown pin with a 10 nF cap to local gnd to avoid any noise pickup.
Frankly it shouldn't be a sensitive node but I'm really puzzled now.

That 'helped' the odd 'jitter' on the hi-side drive. I thought I was on the
home run - I selected the switch position that stops the 3525 outputs and
removed power. A couple of second later the IR2110 went *bang* - well fizzz to
be more accurate - ( no IGBTs danaged though ).

What's weird is that it was the low side driver that went short ! About 2 ohms
from Vs to Lout after it went bust !

try loading them capacitively (perhaps 10-20pF) sans IR2110, see if the
waveforms are still OK.

waveforms are fine sans IR2110.

I'm driven bonkers how the pulse width on OutA and OutB is different whern
it's in circuit ( one presumes there's a clue here but I haven't yet been able
to make any sense of it ). One might assume a load current issue but I have
only 33k from DCbus/2 to the switching point !

set the DC bus to 0V, provide a separate high-side power supply and see
what happens - with no actual output switching, does the problem occur.

I admit - I'm tempted to provide a specific Vboot supply anyway - using a 555
for example.

But this ain't the issue

place a series resistor between the 3525 & 2110, perhaps 1k.

I'll try that !


Cheers, Graham

 

[Terry Given]

Pooh Bear wrote:
[snip]

Good day to you too Terry.




Ummm... guess what I was thinking of doing next ! It's called desperation !





Yuh . That figures. But a 1~2 cm track - with careful attention to routeing ?

perhaps there is a solder short, or noise coupling into that pin. I read
the 3525 datasheet, and its not clear from the block diagram how such an
event might occur, but without looking at a real diagram theres no way
to tell.

Interesting.

there are some Unitrode app notes that talk about this, and IIRC bipolar
output stages are most susceptible, FET output stages are pretty much
immune. Some Unitrode datasheets even say "no output schottky diodes
necessary" but alas I cant recall which ones.

I omitted to mention - for sake of simplicity- that I briefly decoupled the
3525 shutdown pin with a 10 nF cap to local gnd to avoid any noise pickup.
Frankly it shouldn't be a sensitive node but I'm really puzzled now.

That 'helped' the odd 'jitter' on the hi-side drive. I thought I was on the
home run - I selected the switch position that stops the 3525 outputs and
removed power. A couple of second later the IR2110 went *bang* - well fizzz to
be more accurate - ( no IGBTs danaged though ).

What's weird is that it was the low side driver that went short ! About 2 ohms
from Vs to Lout after it went bust !





waveforms are fine sans IR2110.

I'm driven bonkers how the pulse width on OutA and OutB is different whern
it's in circuit ( one presumes there's a clue here but I haven't yet been able
to make any sense of it ). One might assume a load current issue but I have
only 33k from DCbus/2 to the switching point !

true, along with whatever stray capacitance (FETs, layout etc), which
will cause nice fast current spikes and associated LdI/dt voltage
spikes. the dV/dt wont change much at light load (and may even get
worse), so capacitively coupled noise is still there.

does the magnitude of Vdc affect the crazy pulse?

I admit - I'm tempted to provide a specific Vboot supply anyway - using a 555
for example.

But this ain't the issue

my SOP is to provide multiple well-isolated linear power supplies for
every gatedrive, and use those exclusively, until my power stage can
happily drive full load all day. Or at least until I'm happy the
gatedrive really works.

doing this allows you to ignore the charge-pump power supply aspects,
UVLO etc. and just concentrate on banging the gates around.

I'll try that !


Cheers, Graham

bung a lamp in series with the VDC supply, its cheaper than a FET.


Cheers
Terry

PS the PDF offer stills tands.

 

[[email protected]]

Hi, the chip has pulse limiting, a noise pulse generated by the top fet
appearing on pin 10 will reset the pwm latch. Try a hard short from pin
10 to 12. You must also decouple pin 13 (Vc) to ground, 0.1uf should
do. I havent checked the data sheet but 100kHz seems a bit fast for
IR2110.

 

[Tony Williams]

I then find by accident that if I try to 'provoke' the highside
jitter it's affected by my hand capacitance on the switch that I
have included to 'stop switching' to the shutdown pin on the
3525. Uh ? [snip]
I see mismatched timing periods !

I have OUTA used as the high side drive signal . It looked fine
before but it's only 500ns long I discover ! OUTB is 4.5us long (
as it should be ) !

I have no experience of smps supplies, just posting
to register an interest in learning along with you.

Hand capacity effects around the Shutdown input?
A Shutdown input that is both directly connected to the
output OR gates, or is capable of doing an early PWM pulse
termination via the S-R flip flop?

Try sticking a 0.1uF from Shutdown to 0v, right at
the chip?

 

[Pooh Bear]

I then find by accident that if I try to 'provoke' the highside
jitter it's affected by my hand capacitance on the switch that I
have included to 'stop switching' to the shutdown pin on the
3525. Uh ? [snip]
I see mismatched timing periods !

I have OUTA used as the high side drive signal . It looked fine
before but it's only 500ns long I discover ! OUTB is 4.5us long (
as it should be ) !

I have no experience of smps supplies, just posting
to register an interest in learning along with you.

Hand capacity effects around the Shutdown input?
A Shutdown input that is both directly connected to the
output OR gates, or is capable of doing an early PWM pulse
termination via the S-R flip flop?

Try sticking a 0.1uF from Shutdown to 0v, right at
the chip?

Actually I thought 0.1uf was a bit big so I added 10nF there. It had the
desired effect you suggest.

It seemed to stop the 'jitter' on the trailing high side edge but then I
went and switched the damn thing off and the IR2110 went Fizzzz as the
rails decayed ! And it was the the *low* side driver that had gone bad !
It measured 2 ohms form Vs to out after this incident !

My brain is going a bit bonkers.

I'm baffled. Doesn't happen often. Last time I was this perplexed was
when I realised that I had a very fast voltage driver stage in an audio
amplifier that was causing a reverse bias avalanche breakdown problem in
the output devices. And don't even begin to ask how I worked that one
out !

Graham

 

[Pooh Bear]

Hi, the chip has pulse limiting, a noise pulse generated by the top fet
appearing on pin 10 will reset the pwm latch.

OK - I'll look for that but it's the *input* signls to the IR2110 that are
wanky - freaky even ! I keep wondering if I'm probing the correct pin !
It's that bad !

Try a hard short from pin
10 to 12. You must also decouple pin 13 (Vc) to ground, 0.1uf should
do.

Loads of local decoupling.

I havent checked the data sheet but 100kHz seems a bit fast for
IR2110.

Nah - it's not that. Thanks for your interest and input regardless !

Regds, Graham

 

[Tony Williams]

Actually I thought 0.1uf was a bit big so I added 10nF there. It
had the desired effect you suggest.

It seemed to stop the 'jitter' on the trailing high side edge but
then I went and switched the damn thing off and the IR2110 went
Fizzzz as the rails decayed ! And it was the the *low* side
driver that had gone bad ! It measured 2 ohms form Vs to out
after this incident !

I don't seem to see complete threads these days, so
apologies if this remark is out of date.

Perhaps point your bifocals at the 3525 UVLO, and
think about whether it is coming in too late, (on
power-down), and is not making the output stages safe
before the main supply rails drop to a damaging
undervoltage.

 

[Ol' Duffer]

Going entirely from memory...
I thought the SG3525 was a push-pull flyback converter, but
you use terms like "high side driver" and "half bridge", which
make no sense in that context. I can't tell from your scattered
verbal description what you are trying to do, but it sounds fishy.
Got a schematic?

 

[Kristian Ukkonen]

I omitted to mention - for sake of simplicity- that I briefly decoupled the
3525 shutdown pin with a 10 nF cap to local gnd to avoid any noise pickup.
Frankly it shouldn't be a sensitive node but I'm really puzzled now.

"Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation."
Ground pin 10 and see if it helps.

 

[Fred Bloggs]

Hi,

you may have noted my posts about problems recently with my attempts to
make a high power smps.

I'll give a quick overview.

The application is a high power pro-audio amplifier.

Traditional psus use nice toroids that we know well. You can optimise
them for low copper losses that helps keeps weight down.

We want to make our amps lighter though. Like some competitors that are
also using SMPSs.

Various mfrs have used switch-mode techonology. The fixed duty cycle
approach appears to be universal. I expect this is since a classic
forward converter doesn't have the bandwidth to respond to audio
transients. Not to mention cross-regulation to other rails issues.

Unlike most 'forward converters' - see argument about this terminology
another day - PLS ! they run at a fixed duty cycle. I.e. max. Kinda 90%.

Ok - so that's the rough overview.

So - I have this pcb with my design that's 'plain vanilla' - no frills.
The 'control circuitry' i.e. SG 3525 and some other shit is located on a
plug-in pcb via a right-angle pcb header.

I work-up the prototype - the waveforms look right etc etc....

Then I get trouble as I've mentioned here before. The UVLO I can deal
with. If the parts can't 'agree' when to stop working I'll tell them
myself !

So - that one's fixed. Ok - finito. ( or so you might think )

Next problem - apparent 'jitter' on the trailing edge wavefom at the
load ( high side ) with high input volts on the highside drive. I
investigate this. I add a zener clamp on the highside IGBT for example
in case of gate resonance. No good. I modify the signal path to reduce
inductance. No good.

I then find by accident that if I try to 'provoke' the highside jitter
it's affected by my hand capacitance on the switch that I have included
to 'stop switching' to the shutdown pin on the 3525. Uh ?

I check the supervisory supply. I discover that if the supervisory
supply ( provides drive to the 3525 ) is higher than before - changed
transforner ratio - then the jitter occurs earlier ( I'm ramping the
input volts on a variac ).

I'm getting desperate.

So - I look at the 3525 output. OutA and OutB. I checked them earlier
and they look nice and clean.

I have a high resistance nominal load on the half-bridge output that
takes mere milliamps.

I see the switching waveforms. They look sensible at the load. Apart
from this funny 'jitter' on the high side that only occurs at high DC
bus volts when driving my TX ( no sec load ).

I feel I'm going mad.

Finally I get the sense to check the inputs to my IR2110 high side
driver ( from the 3525 ). Recall I checked these before populating the
pcb.

I see mismatched timing periods !

I have OUTA used as the high side drive signal . It looked fine before
but it's only 500ns long I discover ! OUTB is 4.5us long ( as it should
be ) !

I remove the IR2110 gate driver. The waveforms are perfect. Excellent
match between OutA and OutB.

I replace the IR2110. Mismatch occurs again. I've'blown' enough IR2110s
to not think they're the problem. How can the logic input loading of the
IR2110 affect a totem-pole output from the 3525 ?

So - is the 3525 at fault ? I'm careful only to change one item at a
time normally. I reckon maybe I should replace the TI 3525 with an STM
part ( actually that's 2 items at a time technically - but I didn't
expect my other TI sample to be any different ).

I do so. Goddamit if the same bonkers behaviour isn't replicated by
another part from a different vendor !

I check that my pcb man has allocated every pin correctly ( he has ) . I
read the data sheets looking for some mention of erroneous behavour. I
find nothing.

I noted in passing that the 3525 seemed to be sensitive to noise on the
shutdown pin. Odd, since the IC block diagram shows that to be a 'slow'
input. It has to discharge the soft-start cap. Soft-start is working
fine. But my grounds should be clean - I've got a Kelvin connection to
the low-side IGBT emitter mere cm away.

Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !


Graham

If the 500ns OUTA pulse is "clean"- no jitter, then you have something
triggering/resetting that internal FF drive in the 3525. How does that
get there? I haven' looked at the 3525 datasheet, but there are several
avenues: RC timing ckt, feedback, CL shutdown, and maybe some others- it
may take only a 5ns high frequency blip to feedthrough on the wrong hi-z
receptor and off it goes. The high dV/dt's and the proximity suggest
some beading, orientation, distance, and/or shielding may be required
somewhere, but then you already have everything on a board. You can
track this down by probing around for other events while triggering off
the negative edge of OUTA.

 

[Pooh Bear]

I don't seem to see complete threads these days, so
apologies if this remark is out of date.

Perhaps point your bifocals at the 3525 UVLO, and
think about whether it is coming in too late, (on
power-down), and is not making the output stages safe
before the main supply rails drop to a damaging
undervoltage.

Yes, I looked at that area. I'm unhappy it's adequate so I'm intending
to add my own over-riding UVLO that monitors all the rails.

In the instance I mention however I had already asserted the shutdown
function on the 3525 before allowing the rails to decay - i.e. OutA and
B were both inactive. Then the IR2110 expired as the volts dropped !

Graham

 

[Pooh Bear]

"Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation."
Ground pin 10 and see if it helps.

Cheers Kristian. Did that quote come from the data sheet ?

Ok just found it.

Graham

 

[Pooh Bear]

Going entirely from memory...
I thought the SG3525 was a push-pull flyback converter, but
you use terms like "high side driver" and "half bridge", which
make no sense in that context.

The 3525 is simply being used to generate the timing waveforms. The 3525
outputs drive an IR2110 half bridge arrangement.

I can't tell from your scattered verbal description what you are
trying to do, but it sounds fishy.

It's a configuration very similar to one used by one of the major
pro-audio amplifier companies in a mildly different incarnation which
has proven reliability. The differences are modest and I've added some
further protective features in fact.

Got a schematic?

Not that I can post right now sadly.

Graham

 

[Pooh Bear]

If the 500ns OUTA pulse is "clean"- no jitter, then you have something
triggering/resetting that internal FF drive in the 3525.
Indeed.

How does that get there?

Quite !

I haven' looked at the 3525 datasheet, but there are several
avenues: RC timing ckt, feedback, CL shutdown, and maybe some others- it
may take only a 5ns high frequency blip to feedthrough on the wrong hi-z
receptor and off it goes. The high dV/dt's and the proximity suggest
some beading, orientation, distance, and/or shielding may be required
somewhere, but then you already have everything on a board. You can
track this down by probing around for other events while triggering off
the negative edge of OUTA.

After others' comments I'm going to concentate on pin 10 - the shutdown pin.
Despite the fact that the block diagram of the chip's internals shows no
obvious route for this to cause the effect, I've been pointed to a caution on
the data sheet regarding it.

Cheers, Graham

 

[Pooh Bear]

"Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation."
Ground pin 10 and see if it helps.

Lol ! The data sheet application schematic shows the pin hi-Z in normal use !
Time to see the truth I guess ?

Graham

 

[Tony Williams]

Yes, I looked at that area. I'm unhappy it's adequate so I'm
intending to add my own over-riding UVLO that monitors all the
rails.

I'd be tempted to link the Shutdown pin to 0V and
do external shutdown with a clamp across the slow
start capacitor. This would avoid uncontrolled
re-starts if the shutdown command glitched.

Perhaps use a MOSFET with pullup to 12V so that
any global undervoltage circuit has to generate
an active pulldown to keep the 3524 Enabled.

In the instance I mention however I had already asserted the
shutdown function on the 3525 before allowing the rails to decay
- i.e. OutA and B were both inactive. Then the IR2110 expired as
the volts dropped !

The SG3525 data sheet does not say what happens to
the (active) logic-low levels of the OUTs when it's
power supply goes below 8v. At some unknown low
supply voltage the OUTs might go to an open circuit.
Would it be prudent to have safety pull-down R's on
the IR2110 inputs?

 

[Fritz Schlunder]

Hi,

you may have noted my posts about problems recently with my attempts to
make a high power smps.

I'll give a quick overview.

The application is a high power pro-audio amplifier.
....

I noted in passing that the 3525 seemed to be sensitive to noise on the
shutdown pin. Odd, since the IC block diagram shows that to be a 'slow'
input. It has to discharge the soft-start cap. Soft-start is working
fine. But my grounds should be clean - I've got a Kelvin connection to
the low-side IGBT emitter mere cm away.

Right now I feel like I'm going slightly mad. Maybe the pcb guy did
something wacky I've totally missed - but he's rarely that useless.

Does unequal duty cycle on OutA and OutB ring any bells with 3525 users
? It's baffling me !

It sounds like this is for your employment. Therefore my first
recommendation is that you might consider using an off the shelf powersupply
or working with a company that specializes in designing and manufacturing
SMPS designs specially for people such as yourself. You could spend all day
(weeks/months/perhaps even years) banging your head against the wall in
frustration. In the end you might end up with a product that seems reliable
and meets your requirements to your satisfaction only to find in your horror
that once deployed in the field it experiences all sorts of unanticipated
failures. It is very easy to overlook things in an SMPS even when it seems
to be operating well. If you are a generalist doctor (or even a podiatrist)
you probably have no business performing heart transplants when there are
plenty of heart surgeons available.

Nevertheless for your own edutainment it would still be very valuable to
pursue the causes of your current SMPS ailments on your own time.

By the sounds of it your design has multiple weaknesses/problems which may
or may not be directly related to each other.

In particular the IR2110 seems to have attracted your intense scrutiny,
however I would venture to guess it is probably only an innocent victim. As
for the OutA/OutB jitter/unequal pulse width problems (as well as the human
hand near the design and it changes performance), this can probably be
explained by either your implementation of or your understanding of 3525
pins 1, 2, 8, 9, and 10 (for dual inline package). These are all extremely
important pins which are normally driven by relatively high impedance
signals. They are quite sensitive and are quite integral to the control
loop and the general proper functioning of your device.

In particular the shutdown pin is not "slow acting" like you have theorized.
It would appear from the block diagram that even a very momentary high
signal on this pin will instantly turn off the output NOR gates, as well as
set the PWM latch thus keeping the outputs off until at the very least the
next cycle of the oscillator. How fast the outputs turn back on depends on
what happened to the soft start capacitor.

As for your IR2110 fizzling... It seems to me that if the output IGBTs
haven't failed, then clearly something is very wrong. I guess that is
obvious since the IR2110 failed... Without a schematic it is very hard to
say exactly what you are doing and how turning off the 3525 might have
effected the IR2110. What is the nature of your powersupply source for the
3525 and IR2110? Maybe one theory might be the IC bias powersupply is not
properly regulated, and when the 3525 load was removed the voltage overshot
way exceeding the IR2110 absolute maximum rating. Another theory that I
had, but consider quite unlikely, is that perhaps when the 3525 turned off
the output effectively went high impedance, and perhaps stray capacitance
was coupling the output of the IR2110 signal back to the inputs, thus
causing it to oscillate at high frequency. In this case, perhaps the IR2110
internal power dissipation grew too large and it subsequently toasted. I
find this theory unlikely however since the IR2110 inputs have schmitt
triggers and internal pull down resistors, and the input/output phasing
would have to be inverted for this to happen.

Whatever the cause of this problem, it sounds like it has a relatively low
chance of being directly related to your other pulse width/jitter problems.
I would not look directly at the IR2110 for the source of your problem as
much the circuitry surrounding and hooked up to the IR2110 for the root
cause.

Aside from these considerations... Current limiting? You are using it
right? Right?? Without it you are liable to get some kind of STD or
something. Any high power SMPS which has any hope of being remotely
reliable must implement some kind of highly effectual current limiting. The
soft start and shutdown pins of the 3525 may play some role in a given
current limiting implementation, but it is up to you to decide exactly how
best to do it in your application. I personally like implementations that
have two levels of safety. One level instantly shuts off the output as fast
as possible (IE: <1us, preferably <<1us) upon detection of excessive
instantaneous current, but doesn't latch the output off for very long (IE:
perhaps only for the remainder of the given PWM cycle). The other level of
safety measures the time averaged current and shuts the device down for
several cycles upon detection of excessive average current. The fast cycle
by cycle current limit is the best, but unless it is extremely fast it may
not be able to keep the average duty cycle sufficiently small under all
conditions, depending upon how it was implemented. Keep in mind that any
current limiting scheme has the potential to interfere with the voltage
control loop whenever it gets activated.

 

[Fritz Schlunder]

At some unknown low
supply voltage the OUTs might go to an open circuit.
Would it be prudent to have safety pull-down R's on
the IR2110 inputs?

This is a good point, however it appears the designer of the IR2110
envisioned this scenario and took care of it. Presumably the IR2110 inputs
have both schmitt triggers and internal pull downs.