# Biasing a JFET. Measured voltages are not as calculated

Discussion in 'General Electronics Discussion' started by GhostLoveScore, Dec 28, 2016.

1. ### GhostLoveScore

71
5
Nov 27, 2016
I've been playing with this circuit: It's simple tuned FET amplifier. It's not really practical circuit, it's just an example to see if I can calculate how to bias a FET.

Let's begin by writing what I think I know:

Tank circuit is short circuit for DC. Therefore, for calculating bias, drain voltage is 12V
Id=Vcc/R1=4mA
We will choose quiescent point at Id/2 - 2mA.

By using these methods http://www.diyaudio.com/forums/pass-labs/228897-jfet-matching-sorting.html
I measured for my JFET BF244A:
Idss=5.43mA which is about right looking at the datasheet.

Now I have to calculate what Vgs I need to have 2mA drain current. Using upper equation. When I turn it around I can calculate Vgs and I get Vgs=0.86V

That means Vg=Vs+Vgs=6+0.86=6.86V

From that I calculate that in voltage divider I have values from the schematics. But in real life it's not like that. I get right gate voltage, but source voltage is always about 2V off from my calculations. I understand that I my measurement of Idss and Vgs,off may be wrong, but I don't have another way of measuring them.

I tried having 4V at source and then doing the calculations and in practical circuit I got around 6V. If anything, it's always about 2V and I can just do the calculations like that, but I would prefer to know what is happening here.

What am I doing wrong here?

Last edited: Dec 28, 2016
2. ### Harald KappModeratorModerator

10,585
2,360
Nov 17, 2011
O.k.
At this point you ignore Vds!
Or do you mean Idsmax?
What do you mean by Vgs,off? Is this Vth (th for threshold in MOSFETs) or Vp (p for pinch) as it is commonly called? I guess so as this name is used in the fairchild datasheet.
Apart from that, for an N-channel J-FET Vgs, off is negative, the datasheet gives a range from -0.5 V ... -8 V. Your measured value then is Vgs,off = Vp = -2.19 V (note the sign!) and therefore Vgs,bias = -0.86 V
Vs = R1*Ibias = 3 kΩ*2 mA = 6 V
Vgs, bias = Vg,bias - Vs, bias therefore Vg,bias = Vgs, bias + Vs = -0.86 V + 6 V = 5.14 V
Your gate voltage is too high, leading to a higher drain current than expected which in turn results in too high a source voltage.
Also note that the paremeters of the transistor vary e.g. with temperature.

By the way; It helps to use a consistent nomenclature and to observe the signs in your equations.

GhostLoveScore likes this.
3. ### GhostLoveScore

71
5
Nov 27, 2016
Yes, I mean Idsmax
Sorry, it should be pinch off voltage. On different sites people write it differently. I'll use pinch off voltage from now on.

Of course, it was that simple. I read it a hundred times that gate should be negative in respect to source. And then I forget that and make gate positive in respect to source.

I got confused because the pinch off voltage is the same as Vds at which FET goes to saturation mode at Vgs=0.

Last edited: Dec 29, 2016  