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Basic 7 Seg Display circuitry

Discussion in 'Electronic Basics' started by Chippa, Sep 24, 2003.

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  1. Chippa

    Chippa Guest

    I want to drive a 7 segment LED display. I am currently designing the Binary
    to Hex decoder out of AND, OR and NOT gates with the aid of K-maps and truth
    tables. My Question - The display operates with an active low input (low to
    the anode I assume). I have designed my truth table so that 1's appear on
    the segments I want to keep off, and 0's appear on the segments I want to
    turn on for each input combination. What I want to know is if the active low
    means it must be "driven" low?? In other words, should I be driving them low
    with a NOR gate. With my current design, I just have OR gates going to the
    Anodes which just wont give a high output to whichever segments I want to
    TURN ON. Is this ok to do? Or does the NOR gate need to be there instead to
    sink current in the reverse state? Basically when no input is being supplied
    (push buttons give logic high) the seven different OR gates to each segment
    will be giving a high output for DISPLAY of zero (except OR gate to seg 'g'
    of course).. Shall I continue my design, or implement NOR gates instead?

    Cheers
    Chippa
     
  2. Chippa

    Chippa Guest

    Ignore my last line - I meant that - when there is no inputs, the 6 OR gates
    (a, b, c, d, e, f) will be giving a LOW output to display ZERO, not high
    outputs.
     
  3. So, you've got something like a common-anode display:


    a b c d g
    +5-------------x---x---x---x-- ... --x
    | | | | |
    --- --- --- --- ---
    \ / \ / \ / \ / \ /
    --- --- --- --- ---
    | | | | |
    [Ra][Rb][Rc][Rd] [Rg]
    | | | | |
    o o o o o

    I think that will give you the inverse of what you want. Active low =>
    low = ON.
    It might be more economical in gates to decode which segments are
    "off", but I'll leave that to you.

    Best regards,
    Spehro Pefhany
     
  4. budgie

    budgie Guest

    Er, are you doing this for:

    .. a bet
    .. the challenge
    .. a school/uni project
    .. or simply because you like reinventing the wheel?

    It wasn't clear to me from your description whether the display was
    common cathode or common anode. CC usually connected with drivers
    sourcing current, and one side of display (cathodes) grounded. With
    CA, the driver sinks current and the common (anodes) is connected to
    +V.

    If it's CC, unless this falls into one of the above four categories
    I'd go buy a 9368 latch/decoder/driver. Four bit input, and it sets
    the current to 20mA per segment without resistors. About as simple
    and elegant as it gets.

    For CA, there are the 7446, 7447, 74247 and DS8857 to name a few, but
    most require you to set the current. NE587, CA3161E (25mA) and 9374
    also. Some of these may only do 0-9 but I'll bet several do 0-F.
     
  5. John Fields

    John Fields Guest

    Do you really mean binary to HEX decoder? From your description it
    sounds like a binary to seven-segment decoder.

    In any case, as long as you're using a logic family which can sink the
    LED segment current it makes no difference what flavor of gate you use
    to turn the segments ON and OFF with as long as the gate can supply the
    segment current and as long as you present a low to the segment you want
    to be ON. Using a low to turn the LEDs ON means that you'll be sinking
    current and you'll be driving LED _cathodes_, not anodes. You also need
    to make sure that you use a series current limiting resistor for each
    segment, not just one resistor in series with the common anode.

    As far as the combinatorial logic goes, you're free to do whatever you
    have to to make the output follow your truth table. Have fun!
     
  6. Chippa

    Chippa Guest

    Thanks guys,

    Its a school project and I have to show the design from scatch to implement
    it on a FPGA. I agree, and would buy the TTL chip, but this is a small
    project to make ME design a circuit BETWEEN four push buttons (logic 1 when
    pressed) and a 7 segment display (active low connection) - The Xilinx FPGA
    is on a demo board so I am sure all the current limiting resistors etc are
    already in place as is the seven segment power etc etc... Sorry John, you
    are right, binary to Sev Seg, not binary to HEX... I got confused because
    with four inputs I am driving the segments to display A, b, C, d, E, F for
    10 - 15 decimal.. I could have cheated and look at a TTL data sheet for the
    circuitry but wanted to see how simplified I could get it with my own K
    Maps. I have the circuit with 26 AND gates, then into the corresponding 7 OR
    gates. The OR gates go to a, b, c, d, e, f, g on the display. And also 4
    NOT gates alongside each input too... This is as simple as I can get it -
    assuming K Maps reduce to the minimum?? My boolean is not so good when
    comes to factoring etc, but I am assuming that if a K - Map is at its
    simplified minimum there is no room for any more boolean manipulation??
    Also, I just know that it requires a logic low to drive the segments on, so
    I assume the board is set up with a common anode circuit? Appreciate any
    advice

    Thanks Chippa
     
  7. -------------
    None of those are necessary. If you know how a decoder works, you will
    immediately see how to design one without any such brain-overheating
    at all.

    Look here:
    http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS138.gif
    http://www.armory.com/~rstevew/Public/Tutor/Boolean/74LS154.gif
    http://www.armory.com/~rstevew/Public/Tutor/Boolean/7447logic.gif

    http://www.armory.com/~rstevew/Public/Tutor/Displays/7_seg_leds.gif
    http://www.armory.com/~rstevew/Public/Tutor/Displays/hex-7-seg_leds.gif


    -----------------
    LED Displays come in two varieties, common anode and common cathode
    among all the segment LEDs. In the common cathode kind, each LED has
    its cathode tied together, which must be grounded. The common-anode
    kind has each LED's anode tied together, and it is connected to Vcc.
    Then to light one segment, all you need is to ground the other lead
    for that segment through the appropriate resistor, for red LED's
    it is 470 ohm at Vcc = +5VDC .


    I have designed my truth table so that 1's appear on
    ------------
    The outputs should be inverters, or NOR or NAND gates, so that any
    otherwise HI affirmative proposition becomes an affirmative GROUNDING
    of its output pin leading the the common anode LED segment's cathode.
    (Cathod is negative, anode positive).

    -------------
    Only with a common cathode type!

    -------------
    Yes, exactly. Common anode types need cathode drivers to ground.

    -----------
    NORs. See the diagrams of other decoder/demultiplexers above, and
    demuxs are just a kind of decoder.

    Decoders are made with a rank of inverter pairs on the inputs to get
    any input both HI and LO true bus lines, and then the buslines for
    A and /A, B and /B, C and /C, etc, are simply routed to the NANDs or
    NOR as needed to activate that output.

    Especially look at:
    http://www.armory.com/~rstevew/Public/Tutor/Boolean/7447logic.gif

    Since the 74x47's ARE common anode LED driving decoders (74x48 are
    the common cathode LED drivers), and then simply modify it for the
    ABCDEF to suit your purposes!
    Steve
     
  8. Alex Gibson

    Alex Gibson Guest

    fpga or cpld ?


    active low doesn't always mean that common anode has been used
    depends on what parts the designer could get when designing the board.
    Need to check the board and schematics to make sure.

    On the displays look for CA or CC in the part numbers.

    Can also help with simplifying if you use don't cares
    for the ones that don't matter.


    This sort of design is so much easier with vhdl or verilog.
    Also xilinx webpack or ise has a lot less bugs in the hdl parts than in the schematic software.

    hdl - hardware description langauge
    vhdl is descended from ada which descended from pascal.
    verilog is descended from c

    Alex
     
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